[S] Change in coreboot[master]: soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off

[Martin Roth (Code Review)]

Attention is currently required from: Jason Glenesk, Martin L Roth, Fred Reitberger, Felix Held.

Martin Roth has uploaded a new patch set (#2) to the change originally created by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/74527 )

Change subject: soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off
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soc/amd/phoenix: Mark PCIe GPP bridges as hidden instead of off

When one of the General-Purpose PCIe bridges is not used, it doesn't
show up on the PCI bus at all, so coreboot notes it as an issue in the
devicetree. This happens even if the device is marked as off.
To solve this, we're marking the GPP bridge devices in devicetree as
hidden, so they'll only show up in devicetree if they're actually used
on a mainboard.

BUG=b:277997811
TEST=Build

Signed-off-by: Martin Roth 
Change-Id: I7b7577baa2dbb0ea7ebbcdb1a8ae81770e61d76f
---
M src/soc/amd/phoenix/chipset.cb
1 file changed, 30 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74527/2