Hello Hung-Te Lin,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/46386
to review the following change.
Change subject: mb/google/asurada: Add Chrome OS GPIOs ......................................................................
mb/google/asurada: Add Chrome OS GPIOs
Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs.
BUG=None TEST=emerge-asurada coreboot; # also boots into emmc BRANCH=None
Signed-off-by: Hung-Te Lin hungte@chromium.org Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493 --- M src/mainboard/google/asurada/Makefile.inc M src/mainboard/google/asurada/bootblock.c M src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/gpio.h 4 files changed, 48 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46386/1
diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index c742539..02fb830 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -2,12 +2,15 @@
bootblock-y += memlayout.ld bootblock-y += bootblock.c +bootblock-y += chromeos.c
verstage-y += memlayout.ld +verstage-y += chromeos.c verstage-y += reset.c
romstage-y += memlayout.ld romstage-y += boardid.c +romstage-y += chromeos.c romstage-y += romstage.c romstage-y += sdram_configs.c
diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index 3eb05e1..04e8898 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -3,9 +3,12 @@ #include <bootblock_common.h> #include <soc/spi.h>
+#include "gpio.h" + void bootblock_mainboard_init(void) { mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); - //gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); + setup_chromeos_gpios(); + gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index 8f9fa53..18a350b 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -5,16 +5,35 @@ #include <gpio.h> #include <security/tpm/tis.h>
+#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_AP_INT); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_H1_AP_INT); + gpio_input_pullup(GPIO_SD_CD); + gpio_output(GPIO_RESET, 0); +} + void fill_lb_gpios(struct lb_gpios *gpios) { + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, + {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_H1_AP_INT.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {GPIO_SD_CD.id, ACTIVE_HIGH, -1, "SD card detect"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
int get_write_protect_state(void) { - return 0; + return !gpio_get(GPIO_WP); }
int tis_plat_irq_status(void) { - return 0; + return gpio_eint_poll(GPIO_H1_AP_INT); } diff --git a/src/mainboard/google/asurada/gpio.h b/src/mainboard/google/asurada/gpio.h new file mode 100644 index 0000000..90de583 --- /dev/null +++ b/src/mainboard/google/asurada/gpio.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_ASURADA_GPIO_H__ +#define __MAINBOARD_GOOGLE_ASURADA_GPIO_H__ + +#include <soc/gpio.h> + +/* AP_FLASH_WP */ +#define GPIO_WP GPIO(EINT14) +#define GPIO_EC_AP_INT GPIO(EINT5) +#define GPIO_EC_IN_RW GPIO(ANT_SEL8) +#define GPIO_H1_AP_INT GPIO(ANT_SEL9) +/* SD Card Detection */ +#define GPIO_SD_CD GPIO(EINT17) +/* AP_EC_WARM_RST_REQ */ +#define GPIO_RESET GPIO(CAM_PDN2) + +void setup_chromeos_gpios(void); + +#endif
Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46386
to look at the new patch set (#3).
Change subject: mb/google/asurada: Add Chrome OS GPIOs ......................................................................
mb/google/asurada: Add Chrome OS GPIOs
Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs.
BUG=None TEST=emerge-asurada coreboot; # also boots into emmc BRANCH=None
Signed-off-by: Hung-Te Lin hungte@chromium.org Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493 --- M src/mainboard/google/asurada/Makefile.inc M src/mainboard/google/asurada/bootblock.c M src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/gpio.h 4 files changed, 48 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46386/3
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46386 )
Change subject: mb/google/asurada: Add Chrome OS GPIOs ......................................................................
Patch Set 3: Code-Review+2
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46386 )
Change subject: mb/google/asurada: Add Chrome OS GPIOs ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46386/5/src/mainboard/google/asurad... File src/mainboard/google/asurada/chromeos.c:
https://review.coreboot.org/c/coreboot/+/46386/5/src/mainboard/google/asurad... PS5, Line 23: ACTIVE_HIGH ACTIVE_LOW. See http://issuetracker.google.com/issues/171271850.
Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46386
to look at the new patch set (#6).
Change subject: mb/google/asurada: Add Chrome OS GPIOs ......................................................................
mb/google/asurada: Add Chrome OS GPIOs
Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs.
BUG=None TEST=emerge-asurada coreboot; # also boots into emmc BRANCH=None
Signed-off-by: Hung-Te Lin hungte@chromium.org Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493 --- M src/mainboard/google/asurada/Makefile.inc M src/mainboard/google/asurada/bootblock.c M src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/gpio.h 4 files changed, 48 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46386/6
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46386 )
Change subject: mb/google/asurada: Add Chrome OS GPIOs ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46386/5/src/mainboard/google/asurad... File src/mainboard/google/asurada/chromeos.c:
https://review.coreboot.org/c/coreboot/+/46386/5/src/mainboard/google/asurad... PS5, Line 23: ACTIVE_HIGH
ACTIVE_LOW. See http://issuetracker.google.com/issues/171271850.
Ack
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46386 )
Change subject: mb/google/asurada: Add Chrome OS GPIOs ......................................................................
Patch Set 6: Code-Review+2
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46386 )
Change subject: mb/google/asurada: Add Chrome OS GPIOs ......................................................................
Patch Set 6: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46386 )
Change subject: mb/google/asurada: Add Chrome OS GPIOs ......................................................................
mb/google/asurada: Add Chrome OS GPIOs
Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs.
BUG=None TEST=emerge-asurada coreboot; # also boots into emmc BRANCH=None
Signed-off-by: Hung-Te Lin hungte@chromium.org Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46386 Reviewed-by: Yu-Ping Wu yupingso@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/asurada/Makefile.inc M src/mainboard/google/asurada/bootblock.c M src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/gpio.h 4 files changed, 48 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved
diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index c742539..02fb830 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -2,12 +2,15 @@
bootblock-y += memlayout.ld bootblock-y += bootblock.c +bootblock-y += chromeos.c
verstage-y += memlayout.ld +verstage-y += chromeos.c verstage-y += reset.c
romstage-y += memlayout.ld romstage-y += boardid.c +romstage-y += chromeos.c romstage-y += romstage.c romstage-y += sdram_configs.c
diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index cce1438..04e8898 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -3,8 +3,12 @@ #include <bootblock_common.h> #include <soc/spi.h>
+#include "gpio.h" + void bootblock_mainboard_init(void) { mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + setup_chromeos_gpios(); + gpio_eint_configure(GPIO_H1_AP_INT, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c index 8f9fa53..a57392b 100644 --- a/src/mainboard/google/asurada/chromeos.c +++ b/src/mainboard/google/asurada/chromeos.c @@ -5,16 +5,35 @@ #include <gpio.h> #include <security/tpm/tis.h>
+#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_AP_INT); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_H1_AP_INT); + gpio_input_pullup(GPIO_SD_CD); + gpio_output(GPIO_RESET, 0); +} + void fill_lb_gpios(struct lb_gpios *gpios) { + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_IN_RW.id, ACTIVE_LOW, -1, "EC in RW"}, + {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_H1_AP_INT.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {GPIO_SD_CD.id, ACTIVE_HIGH, -1, "SD card detect"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
int get_write_protect_state(void) { - return 0; + return !gpio_get(GPIO_WP); }
int tis_plat_irq_status(void) { - return 0; + return gpio_eint_poll(GPIO_H1_AP_INT); } diff --git a/src/mainboard/google/asurada/gpio.h b/src/mainboard/google/asurada/gpio.h new file mode 100644 index 0000000..90de583 --- /dev/null +++ b/src/mainboard/google/asurada/gpio.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_ASURADA_GPIO_H__ +#define __MAINBOARD_GOOGLE_ASURADA_GPIO_H__ + +#include <soc/gpio.h> + +/* AP_FLASH_WP */ +#define GPIO_WP GPIO(EINT14) +#define GPIO_EC_AP_INT GPIO(EINT5) +#define GPIO_EC_IN_RW GPIO(ANT_SEL8) +#define GPIO_H1_AP_INT GPIO(ANT_SEL9) +/* SD Card Detection */ +#define GPIO_SD_CD GPIO(EINT17) +/* AP_EC_WARM_RST_REQ */ +#define GPIO_RESET GPIO(CAM_PDN2) + +void setup_chromeos_gpios(void); + +#endif
Attention is currently required from: Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46386 )
Change subject: mb/google/asurada: Add Chrome OS GPIOs ......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/google/asurada/chromeos.c:
https://review.coreboot.org/c/coreboot/+/46386/comment/e6f6d8b6_5e1201c6 PS7, Line 25: ACTIVE_HIGH From the schematics, "H1_AP_INT_ODL" should be ACTIVE_LOW, right?
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Hung-Te Lin (Code Review) -
Yidi Lin (Code Review)
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Yu-Ping Wu (Code Review)