Change in coreboot[master]: northbridge/intel/haswell/acpi: Use Printf() for debug prints

[Felix Singer (Code Review)]

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60450 )

Change subject: northbridge/intel/haswell/acpi: Use Printf() for debug prints
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northbridge/intel/haswell/acpi: Use Printf() for debug prints

Change-Id: I3f500ec46a9046a4e8ca50a85965b8e1225f8a33
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60450
Tested-by: build bot (Jenkins) 
Reviewed-by: HAOUAS Elyes 
---
M src/northbridge/intel/haswell/acpi/ctdp.asl
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  HAOUAS Elyes: Looks good to me, approved

diff --git a/src/northbridge/intel/haswell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl
index 565b2d2..bc43a81 100644
--- a/src/northbridge/intel/haswell/acpi/ctdp.asl
+++ b/src/northbridge/intel/haswell/acpi/ctdp.asl
@@ -99,7 +99,7 @@
    		Return (0)
    	}

-		Debug = "Set TDP Down"
+		Printf ("Set TDP Down")

/* Set CTC */
    	CTCS = CTCD
@@ -135,7 +135,7 @@
    		Return (0)
    	}

-		Debug = "Set TDP Nominal"
+		Printf ("Set TDP Nominal")

/* Set PL1 */
    	PL1V = CTDN
@@ -173,7 +173,7 @@
    		Return (0)
    	}

-		Debug = "Enable PL1 Limit"
+		Printf ("Enable PL1 Limit")

/* Set _PPC to LFM */
    	Local0 = PSSS (LFM_)
@@ -201,7 +201,7 @@
    		Return (0)
    	}

-		Debug = "Disable PL1 Limit"
+		Printf ("Disable PL1 Limit")

/* Clear PL1 CLAMP bit */
    	PL1C = 0

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.