Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner.
Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56587 )
Change subject: sc7180: Cleanups for drivers with common clock
......................................................................
Patch Set 2:
(1 comment)
File src/soc/qualcomm/sc7180/display/dsi_phy.c:
https://review.coreboot.org/c/coreboot/+/56587/comment/ef1ac0c4_7da9a7a8
PS1, Line 725: .clk_div = 1, .source_div = 2},
I got the same question as you -- what is this clock and why is it changing?
https://review.coreboot.org/c/coreboot/+/56589/1/src/soc/qualcomm/sc7180/clo...
/*
* client is expected to provide 2n divider value,
* as the divider value in register is in form "2n-1"
*/
mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0;
This was the older convention for display clocks, but now I have moved to use the common macro of DIV, thus need this change.
mdss_clk_cfg.div = half_divider ? DIV(half_divider) : 0;
The divider value expected by earlier driver was in 2n, but now I have updated it to 'n'.
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