Hello Subrata Banik,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/48527
to review the following change.
Change subject: [WIP] [Don't Merge]: PO Safe Config ......................................................................
[WIP] [Don't Merge]: PO Safe Config
Change-Id: I7cce423de924e7056e88b52a2443c554fd9123ac Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48527/1
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index a21ca4a..f176785 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -273,7 +273,7 @@ sizeof(config->PcieRpClkReqDetect));
params->PmSupport = 1; - params->Hwp = 1; + params->Hwp = 0; params->Cx = 1; params->PsOnEnable = 1;
Hello build bot (Jenkins), Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48527
to look at the new patch set (#2).
Change subject: [WIP] [Don't Merge]: PO Safe Config ......................................................................
[WIP] [Don't Merge]: PO Safe Config
Change-Id: I7cce423de924e7056e88b52a2443c554fd9123ac Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48527/2
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48527 )
Change subject: [WIP] [Don't Merge]: PO Safe Config ......................................................................
Patch Set 3:
This change is ready for review.
Attention is currently required from: Tim Wawrzynczak, Meera Ravindranath. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48527 )
Change subject: [WIP] [Don't Merge]: PO Safe Config ......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48527/comment/9c6e9517_2d5e18e3 PS3, Line 118: 0 Instead of setting 0 here as a workaround, can we instead disable RUN_FSP_GOP in config.brya0 until the correct fix is available?
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48527 )
Change subject: [WIP] [Don't Merge]: PO Safe Config ......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48527/comment/97822794_fdeb11b2 PS3, Line 118: 0
Instead of setting 0 here as a workaround, can we instead disable RUN_FSP_GOP in config. […]
Make it 'select MAINBOARD_NO_FSP_GOP' in brya MB ?
Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Meera Ravindranath. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48527 )
Change subject: [WIP] [Don't Merge]: PO Safe Config ......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48527/comment/79187880_4e9d3a1d PS3, Line 118: 0
Make it 'select MAINBOARD_NO_FSP_GOP' in brya MB ?
I think this should be sufficient: https://chromium-review.googlesource.com/c/chromiumos/overlays/chromiumos-ov...
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48527 )
Change subject: [WIP] [Don't Merge]: PO Safe Config ......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48527/comment/e85afdb5_56026354 PS3, Line 118: 0
I think this should be sufficient: https://chromium-review.googlesource. […]
Sure, make a note might be to remove it as we fix the existing issue
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48527
to look at the new patch set (#5).
Change subject: [WIP] [Don't Merge]: PO Safe Config ......................................................................
[WIP] [Don't Merge]: PO Safe Config
Change-Id: I7cce423de924e7056e88b52a2443c554fd9123ac Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48527/5
Attention is currently required from: Furquan Shaikh, Meera Ravindranath. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48527 )
Change subject: [WIP] [Don't Merge]: PO Safe Config ......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5: Is this still needed?
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/48527?usp=email )
Change subject: [WIP] [Don't Merge]: PO Safe Config ......................................................................
Abandoned