Change in ...coreboot[master]: soc/intel/denverton_ns/include/soc/gpio_defs: Fix value of B_PCH_GPIO...
Patrick Havelange has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33573
Change subject: soc/intel/denverton_ns/include/soc/gpio_defs: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
soc/intel/denverton_ns/include/soc/gpio_defs: Fix value of B_PCH_GPIO_RX_SCI_ROUTE
The value for that macro should be 1<<19. This is confirmed by the intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE.
Signed-off-by: Patrick Havelange patrick.havelange@essensium.com Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597 --- M src/soc/intel/denverton_ns/include/soc/gpio_defs.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33573/1
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h index 43e0647..ae61e6d 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h @@ -182,7 +182,7 @@ #define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01
// GPIO Input Route SCI -#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 10) +#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 19) #define N_PCH_GPIO_RX_SCI_ROUTE 19 #define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00 #define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33573 )
Change subject: soc/intel/denverton_ns/include/soc/gpio_defs: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
Patch Set 1: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33573 )
Change subject: soc/intel/denverton_ns/include/soc/gpio_defs: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
Patch Set 1: Code-Review+2
David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33573 )
Change subject: soc/intel/denverton_ns/include/soc/gpio_defs: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
Patch Set 1: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33573 )
Change subject: soc/intel/denverton_ns/include/soc/gpio_defs: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
Patch Set 1: Code-Review+2
(2 comments)
You can edit the commit message in Gerrit, without losing the votes.
https://review.coreboot.org/#/c/33573/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33573/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/denverton_ns/include/soc/gpio_defs: Fix value of B_PCH_GPIO_RX_SCI_ROUTE `soc/intel/dnv` should be enough as prefix, it shouldn't be the full path.
Generally, the summary line should be limited around 55 to 65 chars, 72 chars maximum.
https://review.coreboot.org/#/c/33573/1//COMMIT_MSG@9 PS1, Line 9: The value for that macro should be 1<<19. This is confirmed by the intel doc Should be broken at 72 chars, too.
Hello David Guckian, HAOUAS Elyes, Vanny E, Angel Pons, build bot (Jenkins), Nico Huber, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33573
to look at the new patch set (#2).
Change subject: soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE
The value for that macro should be 1<<19. This is confirmed by the Intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE.
Signed-off-by: Patrick Havelange patrick.havelange@essensium.com Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597 --- M src/soc/intel/denverton_ns/include/soc/gpio_defs.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33573/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33573 )
Change subject: soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/33573/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33573/2//COMMIT_MSG@9 PS2, Line 9: the Intel Maaaybe move this to the next line
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33573 )
Change subject: soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/33573/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33573/2//COMMIT_MSG@10 PS2, Line 10: doc and also by N_PCH_GPIO_RX_SCI_ROUTE. Please add the doc name and revision.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33573 )
Change subject: soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/33573/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33573/2//COMMIT_MSG@10 PS2, Line 10: doc and also by N_PCH_GPIO_RX_SCI_ROUTE.
Please add the doc name and revision.
https://www.intel.com/content/www/us/en/products/docs/processors/atom/c-seri...
Hello David Guckian, HAOUAS Elyes, Vanny E, Angel Pons, build bot (Jenkins), Nico Huber, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33573
to look at the new patch set (#3).
Change subject: soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE
The value for that macro should be 1<<19. This is confirmed by the Intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE. See Intel Atom® Processor C3000 Product Family Datasheet (February 2018) : https://www.intel.com/content/www/us/en/products/docs/processors/atom/c-seri...
Signed-off-by: Patrick Havelange patrick.havelange@essensium.com Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597 --- M src/soc/intel/denverton_ns/include/soc/gpio_defs.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33573/3
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33573 )
Change subject: soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/33573/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33573/3//COMMIT_MSG@15 PS3, Line 15: One blank line is enough.
Hello David Guckian, HAOUAS Elyes, Vanny E, Angel Pons, Paul Menzel, build bot (Jenkins), Nico Huber, David Guckian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33573
to look at the new patch set (#4).
Change subject: soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE
The value for that macro should be 1<<19. This is confirmed by the Intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE. See Intel Atom® Processor C3000 Product Family Datasheet (February 2018) : https://www.intel.com/content/www/us/en/products/docs/processors/atom/c-seri...
Signed-off-by: Patrick Havelange patrick.havelange@essensium.com Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597 --- M src/soc/intel/denverton_ns/include/soc/gpio_defs.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33573/4
Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33573 )
Change subject: soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE ......................................................................
soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE
The value for that macro should be 1<<19. This is confirmed by the Intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE. See Intel Atom® Processor C3000 Product Family Datasheet (February 2018) : https://www.intel.com/content/www/us/en/products/docs/processors/atom/c-seri...
Signed-off-by: Patrick Havelange patrick.havelange@essensium.com Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33573 Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: David Guckian Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/denverton_ns/include/soc/gpio_defs.h 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve HAOUAS Elyes: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved David Guckian: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h index 43e0647..ae61e6d 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h @@ -182,7 +182,7 @@ #define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01
// GPIO Input Route SCI -#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 10) +#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 19) #define N_PCH_GPIO_RX_SCI_ROUTE 19 #define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00 #define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01
-
Angel Pons (Code Review) -
David Guckian (Code Review)
-
Felix Held (Code Review)
-
HAOUAS Elyes (Code Review)
-
Nico Huber (Code Review)
-
Patrick Havelange (Code Review)
-
Paul Menzel (Code Review)