Change in coreboot[master]: soc/amd/common/block/espi_util: Workaround in-band reset race condition - coreboot-gerrit

11 May 2021


      Attention is currently required from: Jason Glenesk, Marshall Dawson, Rob Barnes, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54070 )
Change subject: soc/amd/common/block/espi_util: Workaround in-band reset race condition
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Patch Set 2:
(1 comment)
File src/soc/amd/common/block/lpc/espi_util.c:
https://review.coreboot.org/c/coreboot/+/54070/comment/92737d2c_4ce24183 
PS1, Line 558: workaround
...
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A port 80 write in the middle of espi_setup is another race condition.  […]
Agreed. The PSP has been modified to no longer write port 80s.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I71271377f20eaf29032214be98794e1645d9b70a
Gerrit-Change-Number: 54070
Gerrit-PatchSet: 2
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