Change in coreboot[master]: soc/tigerlake: Make IO decode / enable register configurable

[Sean Rhodes (Code Review)]

Attention is currently required from: Paul Menzel.
Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57140 )

Change subject: soc/tigerlake: Make IO decode / enable register configurable
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Patch Set 15:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/57140/comment/c586062e_bb0362b3 
PS14, Line 9: Would allow
> This allows

Done

https://review.coreboot.org/c/coreboot/+/57140/comment/dde9bb64_5b24c133 
PS14, Line 10: the same way that Skylake can be i.e. register "lpc_ioe"
> Dot/period at the end.

Done

File src/soc/intel/tigerlake/bootblock/pch.c:

https://review.coreboot.org/c/coreboot/+/57140/comment/7b4d1b87_84463236 
PS14, Line 115: 		io_enables = config->lpc_ioe;
> Skylake has: […]

TGL has one 32bit register, previous SOCs had two separate 16bit registers.