Patch merged into coreboot/master: intel/skylake: Implement native Cache-as-RAM (CAR)

the following patch was just integrated into master:
commit fbdc71941454cd4f6dbaebb3e38d27d11ab256ea
Author: Subrata Banik 
Date:   Tue Jan 19 19:19:15 2016 +0530

intel/skylake: Implement native Cache-as-RAM (CAR)

Now coreboot should do BIOS CAR setup along with NEM
    mode setup.

This patch also provides a mechanism to use 16MB code caching
    benefit although LLC still limited to 1M/1.5M based
    on SOC LLC limit.
    Here with unlimited cache line gets replaced. Now we could use
    unlimited cache size along with well defined data size

[pg: updated to current upstream #defines]

BUG=chrome-os-partner:48412
    BRANCH=glados
    TEST=Builds and Boots on FAB4 SKU2/3.

Signed-off-by: Subrata Banik 
    Signed-off-by: pchandri 
    Signed-off-by: Dhaval Sharma

Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b
    Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a
    Original-Reviewed-on: https://chromium-review.googlesource.com/320855
    Original-Commit-Ready: Subrata Banik 
    Original-Tested-by: Subrata Banik 
    Original-Reviewed-by: Aaron Durbin 
    Reviewed-on: https://review.coreboot.org/13138
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth

See https://review.coreboot.org/13138 for details.

-gerrit