Change in coreboot[master]: tpch: Introduce new thermal control mechanism for pch device

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar, Patrick Rudolph, Karthik Ramasubramanian.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57096 )

Change subject: tpch: Introduce new thermal control mechanism for pch device
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Patch Set 1:

(4 comments)

Patchset:

PS1: 
Why did you break this out into a separate chip driver?

I think this support could be handled within the existing DPTF driver.

e.g.,

1) a new Kconfig (e.g., DRIVERS_INTEL_DPTF_SUPPORTS_TPCH) because this requires PMC_IPC_ACPI_INTERFACE support, which AFAIK not all platforms that use the DPTF driver support (google/hatch, CML for example I don't know if supports the PMC IPC ACPI interface or not)

```
config DRIVERS_INTEL_DPTF_SUPPORTS_TPCH
       def_bool n
       depends on PMC_IPC_ACPI_INTERFACE
       ...
```

2) Add the TPCH device HID to the dptf_platform_info object

3) Then the DPTF chip driver can automatically write out the TPCH device and its methods, etc. when the Kconfig is selected, e.g.:

```
if (CONFIG(DRIVERS_INTEL_DPTF_SUPPORTS_TPCH)) {
    write_tpch_device();
    write_tpch_methods();
    ....
}
```

File src/drivers/intel/tpch/tpch.h:

https://review.coreboot.org/c/coreboot/+/57096/comment/7263257d_392bf487 
PS1, Line 15: /* IPC command to control FIVR Configuration */
            : #define	V_PMC_PWRM_IPC_CMD_COMMAND_FIVR			0xA3
            : /* IPC subcommand to write FIVR Register */
            : #define	V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_WRITE	0x01
            : /* IPC subcommand to control RFI Control 0 register logic write */
            : #define	V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL0_LOGIC	0x00
            : /* IPC subcommand to control RFI Control 4 register logic write */
            : #define V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL4_LOGIC	0x01
These should probably go in 
`src/soc/intel/common/block/include/intelblocks/pmc_ipc.h`

File src/drivers/intel/tpch/tpch.c:

https://review.coreboot.org/c/coreboot/+/57096/comment/7771c365_a852612d 
PS1, Line 26: 	acpigen_emit_namestring("IPCS");
            : 	acpigen_write_integer(V_PMC_PWRM_IPC_CMD_COMMAND_FIVR);
            : 	acpigen_write_integer(V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_WRITE);
            : 	acpigen_write_integer(0x8);
            : 	acpigen_write_integer(V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL0_LOGIC);
            : 	acpigen_write_dword(3);
            : 	acpigen_emit_byte(RETURN_OP);
            : 	acpigen_write_package(0);
            : 	acpigen_write_method_end();
            : 	acpigen_pop_len();
            : 
            : 	acpigen_write_method_serialized("RFC1", 1);
            : 	acpigen_emit_namestring("IPCS");
            : 	acpigen_write_integer(V_PMC_PWRM_IPC_CMD_COMMAND_FIVR);
            : 	acpigen_write_integer(V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_WRITE);
            : 	acpigen_write_integer(0x8);
            : 	acpigen_write_integer(V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL4_LOGIC);
Is there any documentation on these IPC commands?

Also this means that this driver now requires the ACPI PMC IPC functionality to be available, meaning this Kconfig option also has to `depends on PMC_IPC_ACPI_INTERFACE` as well.

https://review.coreboot.org/c/coreboot/+/57096/comment/bd536692_2b5d8375 
PS1, Line 51: devices
nit: space after `devices`