Change in coreboot[master]: crossgcc: Upgrade GCC to 10.1.0

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HAOUAS Elyes (Code Review)

10 Jun 2020 10 Jun '20

4:59 p.m.

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.1.0 ......................................................................

crossgcc: Upgrade GCC to 10.1.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.1.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.1.0_gnat.patch R util/crossgcc/patches/gcc-10.1.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.1.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 9 files changed, 2 insertions(+), 21,441 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/1

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HAOUAS Elyes (Code Review)

10 Jun 10 Jun

5:06 p.m.

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.1.0 ......................................................................

Patch Set 1:

tested with qemu: === qemu-system-x86_64 -bios build/coreboot.rom -serial stdio

coreboot-4.12-635-g322cab4277 Wed Jun 10 16:55:02 UTC 2020 bootblock starting (log level: 7)... FMAP: Found "FLASH" version 1.1 at 0x0. FMAP: base = 0xfffc0000 size = 0x40000 #areas = 3 FMAP: area COREBOOT found @ 200 (261632 bytes) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 3954 BS: bootblock times (exec / console): total (unknown) / 0 ms

coreboot-4.12-635-g322cab4277 Wed Jun 10 16:55:02 UTC 2020 romstage starting (log level: 7)... QEMU: firmware config interface detected Firmware config version id: 3 CBMEM: IMD: root @ 0x07fff000 254 entries. IMD: root @ 0x07ffec00 62 entries. MTRR Range: Start=fffc0000 End=0 (Size 40000) FMAP: area COREBOOT found @ 200 (261632 bytes) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset 11340 size 3e30 Decompressing stage fallback/postcar @ 0x07fd3fc0 (32432 bytes) Loading module at 0x07fd4000 with entry 0x07fd4000. filesize: 0x3b90 memsize: 0x7e70 Processing 145 relocs. Offset value of 0x05fd4000 BS: romstage times (exec / console): total (unknown) / 16 ms

coreboot-4.12-635-g322cab4277 Wed Jun 10 16:55:02 UTC 2020 postcar starting (log level: 7)... FMAP: area COREBOOT found @ 200 (261632 bytes) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 3a40 size c209 Decompressing stage fallback/ramstage @ 0x07faefc0 (144912 bytes) Loading module at 0x07faf000 with entry 0x07faf000. filesize: 0x18858 memsize: 0x235d0 Processing 1516 relocs. Offset value of 0x071af000 BS: postcar times (exec / console): total (unknown) / 11 ms

coreboot-4.12-635-g322cab4277 Wed Jun 10 16:55:02 UTC 2020 ramstage starting (log level: 7)... Enumerating buses... Root Device scanning... CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled CPU_CLUSTER: 0 scanning... QEMU: firmware config interface detected Firmware config version id: 3 QEMU: max_cpus is 1 CPU: APIC: 00 enabled scan_bus: bus CPU_CLUSTER: 0 finished in 3 msecs DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] enabled PCI: 00:01.1 [8086/7010] enabled PCI: 00:01.3 [8086/7113] enabled PCI: 00:02.0 [1234/1111] enabled PCI: 00:03.0 [8086/100e] enabled PCI: 00:01.0 scanning... scan_bus: bus PCI: 00:01.0 finished in 0 msecs PCI: 00:01.3 scanning... scan_bus: bus PCI: 00:01.3 finished in 0 msecs scan_bus: bus DOMAIN: 0000 finished in 10 msecs scan_bus: bus Root Device finished in 19 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 7 / 16 ms found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... QEMU: e820/ram: 0x00000000 + 0x08000000 QEMU: reserve ioports 0x0510-0x0511 [firmware-config] QEMU: reserve ioports 0x5658-0x5658 [vmware-port] QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug] QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug] QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0] Done reading resources. ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff update_constraints: DOMAIN: 0000 0c base 00000510 limit 00000511 io (fixed) update_constraints: DOMAIN: 0000 0d base 00005658 limit 00005658 io (fixed) update_constraints: DOMAIN: 0000 0e base 0000ae00 limit 0000ae0f io (fixed) update_constraints: DOMAIN: 0000 0f base 0000af00 limit 0000af1f io (fixed) update_constraints: DOMAIN: 0000 10 base 0000afe0 limit 0000afe3 io (fixed) update_constraints: PCI: 00:01.0 01 base 00000000 limit 00000fff io (fixed) update_constraints: PCI: 00:01.3 01 base 0000e400 limit 0000e43f io (fixed) update_constraints: PCI: 00:01.3 02 base 00000f00 limit 00000f0f io (fixed) DOMAIN: 0000: Resource ranges: * Base: 1000, Size: 4658, Tag: 100 * Base: 5659, Size: 57a7, Tag: 100 * Base: ae10, Size: f0, Tag: 100 * Base: af20, Size: c0, Tag: 100 * Base: afe4, Size: 341c, Tag: 100 * Base: e440, Size: 1bc0, Tag: 100 PCI: 00:03.0 14 * [0x1000 - 0x103f] limit: 103f io PCI: 00:01.1 20 * [0x1040 - 0x104f] limit: 104f io DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffffff update_constraints: DOMAIN: 0000 0a base 00000000 limit 0009ffff mem (fixed) update_constraints: DOMAIN: 0000 0b base 000c0000 limit 07ffffff mem (fixed) update_constraints: DOMAIN: 0000 11 base 000a0000 limit 000bffff mem (fixed) update_constraints: DOMAIN: 0000 12 base 000c0000 limit 000fffff mem (fixed) update_constraints: DOMAIN: 0000 02 base fec00000 limit fecfffff mem (fixed) update_constraints: DOMAIN: 0000 03 base fee00000 limit fee0ffff mem (fixed) update_constraints: PCI: 00:01.0 02 base ff800000 limit ffffffff mem (fixed) DOMAIN: 0000: Resource ranges: * Base: 8000000, Size: f6c00000, Tag: 200 * Base: fed00000, Size: 100000, Tag: 200 * Base: fee10000, Size: 9f0000, Tag: 200 * Base: 100000000, Size: ff00000000, Tag: 100200 PCI: 00:02.0 10 * [0x8000000 - 0x8ffffff] limit: 8ffffff prefmem PCI: 00:03.0 30 * [0x9000000 - 0x903ffff] limit: 903ffff mem PCI: 00:03.0 10 * [0x9040000 - 0x905ffff] limit: 905ffff mem PCI: 00:02.0 30 * [0x9060000 - 0x906ffff] limit: 906ffff mem PCI: 00:02.0 18 * [0x9070000 - 0x9070fff] limit: 9070fff mem DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffffff done === Resource allocator: DOMAIN: 0000 - resource allocation complete === PCI: 00:01.1 20 <- [0x0000001040 - 0x000000104f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x0008000000 - 0x0008ffffff] size 0x01000000 gran 0x18 prefmem PCI: 00:02.0 18 <- [0x0009070000 - 0x0009070fff] size 0x00001000 gran 0x0c mem PCI: 00:02.0 30 <- [0x0009060000 - 0x000906ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 10 <- [0x0009040000 - 0x000905ffff] size 0x00020000 gran 0x11 mem PCI: 00:03.0 14 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io PCI: 00:03.0 30 <- [0x0009000000 - 0x000903ffff] size 0x00040000 gran 0x12 romem Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 15 / 73 ms Enabling resources... PCI: 00:00.0 cmd <- 00 PCI: 00:01.0 cmd <- 00 PCI: 00:01.1 cmd <- 01 PCI: 00:01.3 cmd <- 00 PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 cmd <- 03 done. BS: BS_DEV_ENABLE run times (exec / console): 4 / 3 ms Initializing devices... CPU_CLUSTER: 0 init Initializing CPU #0 CPU: vendor AMD device 663 CPU: family 06, model 06, stepping 03 Setting up local APIC... apic_id: 0x00 done. CPU #0 initialized CPU_CLUSTER: 0 init finished in 4 msecs PCI: 00:00.0 init Assigning IRQ 10 to PCI: 00:01.3 Assigning IRQ 11 to PCI: 00:03.0 PCI: 00:00.0 init finished in 6 msecs PCI: 00:01.0 init RTC Init PCI: 00:01.0 init finished in 2 msecs PCI: 00:01.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: off PCI: 00:01.1 init finished in 2 msecs PCI: 00:02.0 init PCI: 00:02.0 init finished in 15 msecs PCI: 00:03.0 init PCI: 00:03.0 init finished in 0 msecs Devices initialized BS: BS_DEV_INIT run times (exec / console): 25 / 15 ms Finalize devices... Devices finalized BS: BS_POST_DEVICE run times (exec / console): 1 / 285 ms Copying Interrupt Routing Table to 0x000f0000... done. Copying Interrupt Routing Table to 0x07fa5000... done. PIRQ table: 128 bytes. QEMU: found ACPI tables in fw_cfg. QEMU: loading "etc/acpi/rsdp" to 0x7f81000 (len 20) QEMU: loading "etc/acpi/tables" to 0x7f81040 (len 131072) QEMU: loaded ACPI tables from fw_cfg. Looking on 0x07f81000 for valid checksum Checksum 1 passed Checksum 2 passed all OK ACPI: * SSDT Found 1 CPU(s). ACPI: added table 4/32, length now 52 ACPI tables: 131136 bytes. smbios_write_tables: 07f80000 SMBIOS: Unknown CPU DOMAIN: 0000 (QEMU Northbridge i440fx) QEMU: found smbios tables in fw_cfg (len 321). QEMU: coreboot type0 table found at 0x7f80020. QEMU: loading smbios tables to 0x7f80064 SMBIOS tables: 421 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 97e4 Writing coreboot table at 0x07fa6000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000007f7ffff: RAM 4. 0000000007f80000-0000000007faefff: CONFIGURATION TABLES 5. 0000000007faf000-0000000007fd2fff: RAMSTAGE 6. 0000000007fd3000-0000000007ffffff: CONFIGURATION TABLES 7. 00000000ff800000-00000000ffffffff: RESERVED FMAP: area COREBOOT found @ 200 (261632 bytes) Wrote coreboot table at: 0x07fa6000, 0x2a0 bytes, checksum 6e39 coreboot table: 696 bytes. IMD ROOT 0. 0x07fff000 0x00001000 IMD SMALL 1. 0x07ffe000 0x00001000 CONSOLE 2. 0x07fde000 0x00020000 TIME STAMP 3. 0x07fdd000 0x00000910 ROMSTG STCK 4. 0x07fdc000 0x00001000 AFTER CAR 5. 0x07fd3000 0x00009000 RAMSTAGE 6. 0x07fae000 0x00025000 COREBOOT 7. 0x07fa6000 0x00008000 IRQ TABLE 8. 0x07fa5000 0x00001000 ACPI 9. 0x07f81000 0x00024000 SMBIOS 10. 0x07f80000 0x00000800 IMD small region: IMD ROOT 0. 0x07ffec00 0x00000400 FMAP 1. 0x07ffeb40 0x000000b6 BS: BS_WRITE_TABLES run times (exec / console): 33 / 42 ms FMAP: area COREBOOT found @ 200 (261632 bytes) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 151c0 size 10eec Checking segment from ROM address 0xfffd53f8 Payload being loaded at below 1MiB without region being marked as RAM usable. Checking segment from ROM address 0xfffd5414 Loading segment from ROM address 0xfffd53f8 code (compression=1) New segment dstaddr 0x000dfce0 memsize 0x20320 srcaddr 0xfffd5430 filesize 0x10eb4 Loading Segment: addr: 0x000dfce0 memsz: 0x0000000000020320 filesz: 0x0000000000010eb4 using LZMA Loading segment from ROM address 0xfffd5414 Entry Point 0x000fd25f BS: BS_PAYLOAD_LOAD run times (exec / console): 108 / 13 ms Jumping to boot code at 0x000fd25f(0x07fa6000) SeaBIOS (version rel-1.13.0-0-gf21b5a4) BUILD: gcc: (coreboot toolchain v866e9e5cf7 2020-05-14) 10.1.0 binutils: (GNU Binutils) 2.34 SeaBIOS (version rel-1.13.0-0-gf21b5a4) BUILD: gcc: (coreboot toolchain v866e9e5cf7 2020-05-14) 10.1.0 binutils: (GNU Binutils) 2.34 Found coreboot cbmem console @ 7fde000 Found mainboard Emulation QEMU x86 i440fx/piix4 Relocating init from 0x000e1400 to 0x07f32d00 (size 53856) Found CBFS header at 0xfffc0238 multiboot: eax=7fc73a0, ebx=7fc7364 Found 6 PCI devices (max PCI bus is 00) Copying SMBIOS entry point from 0x07f80000 to 0x000f6340 Copying ACPI RSDP from 0x07f81000 to 0x000f6320 Copying PIR from 0x07fa5000 to 0x000f62a0 Using pmtimer, ioport 0xe408 Scan for VGA option rom Running option rom at c000:0003 pmm call arg1=0 Turning on vga text mode console SeaBIOS (version rel-1.13.0-0-gf21b5a4) ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9) ATA controller 2 at 170/374/0 (irq 15 dev 9) Found 1 lpt ports Found 1 serial ports DVD/CD [ata1-0: QEMU DVD-ROM ATAPI-4 DVD/CD] Searching bootorder for: /pci@i0cf8/*@1,1/drive@1/disk@0 Searching bios-geometry for: /pci@i0cf8/*@1,1/drive@1/disk@0 PS2 keyboard initialized All threads complete. Scan for option roms Running option rom at ca00:0003 pmm call arg1=1 pmm call arg1=0 pmm call arg1=1 pmm call arg1=0 Searching bootorder for: /pci@i0cf8/*@3

Press ESC for boot menu.

Searching bootorder for: HALT Space available for UMB: cb000-ed000, f5b60-f6200 Returned 262144 bytes of ZoneHigh e820 map has 6 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 0000000007f80000 = 1 RAM 4: 0000000007f80000 - 0000000008000000 = 2 RESERVED 5: 00000000ff800000 - 0000000100000000 = 2 RESERVED enter handle_19: NULL Booting from DVD/CD... Device reports MEDIUM NOT PRESENT scsi_is_ready returned -1 Boot failed: Could not read from CDROM (code 0003) enter handle_18: NULL Booting from ROM... Booting from ca00:0385 enter handle_18: NULL Booting from Floppy... Boot failed: could not read the boot disk

enter handle_18: NULL Booting from Hard Disk... Boot failed: could not read the boot disk

enter handle_18: NULL No bootable device. Retrying in 60 seconds.

HAOUAS Elyes (Code Review)

5:07 p.m.

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.1.0 ......................................................................

Patch Set 1:

tested also on (i945GC/ich7) based board and it boots

HAOUAS Elyes (Code Review)

7:58 p.m.

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.1.0 ......................................................................

Patch Set 1:

with "payload = none": === coreboot-4.12-635-g322cab4277 Wed Jun 10 16:55:02 UTC 2020 bootblock starting (log level: 7)... ARM64: Exception handlers installed. Backing address range [0x00000000:0x1000000000000) with new page table @0x60070000 Mapping address range [0x00000000:0x40000000) as cacheable | read-write | secure | device Backing address range [0x00000000:0x8000000000) with new page table @0x60071000 Mapping address range [0x40000000:0x80000000) as cacheable | read-write | secure | normal Mapping address range [0x60070000:0x60090000) as cacheable | read-write | secure | normal Backing address range [0x40000000:0x80000000) with new page table @0x60072000 Backing address range [0x60000000:0x60200000) with new page table @0x60073000 Mapping address range [0x60010000:0x60020000) as cacheable | read-write | secure | normal Mapping address range [0x60030000:0x60050000) as cacheable | read-write | secure | normal Mapping address range [0x600b0000:0x610b0000) as cacheable | read-write | secure | normal Backing address range [0x61000000:0x61200000) with new page table @0x60074000 Mapping address range [0x0e000000:0x0f000000) as cacheable | read-write | secure | normal Backing address range [0x00000000:0x40000000) with new page table @0x60075000 FMAP: Found "FLASH" version 1.1 at 0x20000. FMAP: base = 0x0 size = 0x400000 #areas = 4 FMAP: area COREBOOT found @ 20200 (4062720 bytes) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 31d3 BS: bootblock times (exec / console): total (unknown) / 31 ms

coreboot-4.12-635-g322cab4277 Wed Jun 10 16:55:02 UTC 2020 romstage starting (log level: 7)... ARM64: Exception handlers installed. RAMDETECT: Found 892 MiB RAM CBMEM: IMD: root @ 0x77bff000 254 entries. IMD: root @ 0x77bfec00 62 entries. FMAP: area COREBOOT found @ 20200 (4062720 bytes) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 32c0 size 4ad8 BS: romstage times (exec / console): total (unknown) / 7 ms

coreboot-4.12-635-g322cab4277 Wed Jun 10 16:55:02 UTC 2020 ramstage starting (log level: 7)... ARM64: Exception handlers installed. Enumerating buses... RAMDETECT: Found 892 MiB RAM Root Device scanning... CPU_CLUSTER: 0 enabled scan_bus: bus Root Device finished in 0 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 4 / 2 ms Allocating resources... Reading resources... CPU_CLUSTER: 0 missing read_resources Done reading resources. Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 1 / 2 ms Enabling resources... done. BS: BS_DEV_ENABLE run times (exec / console): 1 / 0 ms Initializing devices... Devices initialized BS: BS_DEV_INIT run times (exec / console): 0 / 1 ms Finalize devices... Devices finalized BS: BS_POST_DEVICE run times (exec / console): 1 / 0 ms Writing coreboot table at 0x77bdc000 0. 000000000e000000-000000000effffff: BL31 1. 0000000040000000-000000006001ffff: RAM 2. 0000000060020000-000000006002ffff: RAMSTAGE 3. 0000000060030000-000000006006ffff: RAM 4. 0000000060070000-000000006008ffff: RAMSTAGE 5. 0000000060090000-00000000600affff: RAM 6. 00000000600b0000-00000000600c3fff: RAMSTAGE 7. 00000000600c4000-0000000077bdbfff: RAM 8. 0000000077bdc000-0000000077bfffff: CONFIGURATION TABLES FMAP: area COREBOOT found @ 20200 (4062720 bytes) Wrote coreboot table at: 0x77bdc000, 0x19c bytes, checksum adb5 coreboot table: 436 bytes. IMD ROOT 0. 0x77bff000 0x00001000 IMD SMALL 1. 0x77bfe000 0x00001000 CONSOLE 2. 0x77bde000 0x00020000 COREBOOT 3. 0x77bdc000 0x00002000 IMD small region: IMD ROOT 0. 0x77bfec00 0x00000400 FMAP 1. 0x77bfeb20 0x000000e0 BS: BS_WRITE_TABLES run times (exec / console): 7 / 8 ms FMAP: area COREBOOT found @ 20200 (4062720 bytes) CBFS: Locating 'fallback/payload' CBFS: 'fallback/payload' not found. Payload not loaded.

HAOUAS Elyes (Code Review)

8:35 p.m.

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.1.0 ......................................................................

Abandoned

I don't know how to check on qemu-aarm64

HAOUAS Elyes (Code Review)

12 Jun 12 Jun

5:54 a.m.

HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.1.0 ......................................................................

Restored

Paul Menzel (Code Review)

16 Jun 16 Jun

6:58 a.m.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.1.0 ......................................................................

Patch Set 5:

For testing ARM systems, please take a look at the proposed integration tests of u-root [1]. There is a Linux kernel configuration file, which should be able to boot.

[1]: https://github.com/u-root/u-root/pull/1708/files

HAOUAS Elyes (Code Review)

9:26 a.m.

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.1.0 ......................................................................

Patch Set 5:

...

Patch Set 5:

For testing ARM systems, please take a look at the proposed integration tests of u-root [1]. There is a Linux kernel configuration file, which should be able to boot.

Thank you. even if it boots, we can't merge current change. We need to fix CB:42306 , CB:42305 and CB:42299 before.

Any takers?

HAOUAS Elyes (Code Review)

23 Jul 23 Jul

12:13 p.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42251

to look at the new patch set (#11).

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

crossgcc: Upgrade GCC to 10.2.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

changes: https://gcc.gnu.org/gcc-10/changes.html

Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.2.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.2.0_gnat.patch R util/crossgcc/patches/gcc-10.2.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.2.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 9 files changed, 2 insertions(+), 21,441 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/11

HAOUAS Elyes (Code Review)

24 Jul 24 Jul

7 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42251

to look at the new patch set (#12).

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

crossgcc: Upgrade GCC to 10.2.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

Some changes: https://gcc.gnu.org/gcc-10/changes.html

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/12

KOUAM Ledoux (Code Review)

10:12 p.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

KOUAM Ledoux has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 12:

gcc9 doesn't croos for boting with qemu-i686 , aarch64 and so on ... i think it is working gcc9 (crossing for i386) with qemu i386 only

...

so i thin that gcc9 is broken , so upgrade GCC will be useful ...

Nice

HAOUAS Elyes (Code Review)

25 Jul 25 Jul

6 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 12:

...

Patch Set 12:

gcc9 doesn't croos for boting with qemu-i686 , aarch64 and so on ...

You mean "boot"?

...

i think it is working gcc9 (crossing for i386) with qemu i386 only

so i thin that gcc9 is broken , so upgrade GCC will be useful

Nice

we already know that quemu-aarch64 will not boot when the rom file is built using gcc-9 toolchain. what would be nice is to build quemu-aarch64(virt) rom file using current patch a check if it will boot or not.

Patrick Georgi (Code Review)

18 Aug 18 Aug

1:50 p.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 14:

This needs coordination with the KASAN patch. Harshit, any idea how hard it will be to port the gcc patch to gcc 10?

Harshit Sharma (Code Review)

19 Aug 19 Aug

12:27 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 14:

...

Patch Set 14:

This needs coordination with the KASAN patch. Harshit, any idea how hard it will be to port the gcc patch to gcc 10?

Actually, I already have a patch file ready which would be compatible with gcc 10.2.0. I created it with the intention of convincing gcc developers to include this feature. You can find it here: https://gcc.gnu.org/pipermail/gcc-patches/2020-July/550176.html

HAOUAS Elyes (Code Review)

6:29 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Hello build bot (Jenkins), Patrick Georgi, Harshit Sharma,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42251

to look at the new patch set (#15).

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

crossgcc: Upgrade GCC to 10.2.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

Some changes: https://gcc.gnu.org/gcc-10/changes.html

Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.2.0_ada-musl_workaround.patch A util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-10.2.0_gnat.patch R util/crossgcc/patches/gcc-10.2.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_asan_shadow_offset_callback.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.2.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 11 files changed, 112 insertions(+), 21,550 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/15

Harshit Sharma (Code Review)

7:43 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 15:

(2 comments)

https://review.coreboot.org/c/coreboot/+/42251/15/util/crossgcc/patches/gcc-... File util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch:

https://review.coreboot.org/c/coreboot/+/42251/15/util/crossgcc/patches/gcc-... PS15, Line 52: @@ asan_emit_stack_protection (rtx base, rtx pbase, : unsigned int alignb, Hey Elyes, I believe it would give an error while patching. I think the alignment somewhat messed up when I pushed the patch on their mailing list. Let me share the original patch file with you. Can I upload it directly here?

https://review.coreboot.org/c/coreboot/+/42251/15/util/crossgcc/patches/gcc-... PS15, Line 95: Init(7000) Param Optimization Same here

HAOUAS Elyes (Code Review)

8:41 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 15:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42251/15/util/crossgcc/patches/gcc-... File util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch:

https://review.coreboot.org/c/coreboot/+/42251/15/util/crossgcc/patches/gcc-... PS15, Line 52: @@ asan_emit_stack_protection (rtx base, rtx pbase, : unsigned int alignb,

...

Hey Elyes, I believe it would give an error while patching. […]

sure, please feel free to upload inhere :)

-- To view, visit https://review.coreboot.org/c/coreboot/+/42251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Gerrit-Change-Number: 42251 Gerrit-PatchSet: 15 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Harshit Sharma harshitsharmajs@gmail.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: KOUAM Ledoux kouamdoux@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 19 Aug 2020 08:41:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Harshit Sharma harshitsharmajs@gmail.com Gerrit-MessageType: comment

Harshit Sharma (Code Review)

9:05 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Harshit Sharma has uploaded a new patch set (#16) to the change originally created by HAOUAS Elyes. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

crossgcc: Upgrade GCC to 10.2.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

Some changes: https://gcc.gnu.org/gcc-10/changes.html

Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.2.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-10.2.0_gnat.patch R util/crossgcc/patches/gcc-10.2.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.2.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 10 files changed, 26 insertions(+), 21,480 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/16

Harshit Sharma (Code Review)

9:12 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Harshit Sharma has uploaded a new patch set (#17) to the change originally created by HAOUAS Elyes. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

crossgcc: Upgrade GCC to 10.2.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

Some changes: https://gcc.gnu.org/gcc-10/changes.html

Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.2.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-10.2.0_gnat.patch R util/crossgcc/patches/gcc-10.2.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.2.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 10 files changed, 24 insertions(+), 21,479 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/17

Harshit Sharma (Code Review)

9:13 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 17:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42251/15/util/crossgcc/patches/gcc-... File util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch:

https://review.coreboot.org/c/coreboot/+/42251/15/util/crossgcc/patches/gcc-... PS15, Line 52: @@ asan_emit_stack_protection (rtx base, rtx pbase, : unsigned int alignb,

...

sure, please feel free to upload inhere :)

Done.

-- To view, visit https://review.coreboot.org/c/coreboot/+/42251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Gerrit-Change-Number: 42251 Gerrit-PatchSet: 17 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Harshit Sharma harshitsharmajs@gmail.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: KOUAM Ledoux kouamdoux@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 19 Aug 2020 09:13:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes ehaouas@noos.fr Comment-In-Reply-To: Harshit Sharma harshitsharmajs@gmail.com Gerrit-MessageType: comment

Harshit Sharma (Code Review)

9:28 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Harshit Sharma has uploaded a new patch set (#18) to the change originally created by HAOUAS Elyes. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

crossgcc: Upgrade GCC to 10.2.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

Some changes: https://gcc.gnu.org/gcc-10/changes.html

Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.2.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-10.2.0_gnat.patch R util/crossgcc/patches/gcc-10.2.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.2.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 10 files changed, 20 insertions(+), 21,475 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/18

HAOUAS Elyes (Code Review)

3:09 p.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 20:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42251/15/util/crossgcc/patches/gcc-... File util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch:

https://review.coreboot.org/c/coreboot/+/42251/15/util/crossgcc/patches/gcc-... PS15, Line 95: Init(7000) Param Optimization

...

Same here

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/42251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Gerrit-Change-Number: 42251 Gerrit-PatchSet: 20 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Harshit Sharma harshitsharmajs@gmail.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: KOUAM Ledoux kouamdoux@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 19 Aug 2020 15:09:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Harshit Sharma harshitsharmajs@gmail.com Gerrit-MessageType: comment

Nico Huber (Code Review)

3:18 p.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 20: Code-Review+1

LGTM. Can we confirm that

a) the upstream NDS32 ITE support is sufficient, and b) the FIT loader on ARM is indeed working (with patched `list.h`)?

-- To view, visit https://review.coreboot.org/c/coreboot/+/42251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Gerrit-Change-Number: 42251 Gerrit-PatchSet: 20 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Harshit Sharma harshitsharmajs@gmail.com Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: KOUAM Ledoux kouamdoux@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Wed, 19 Aug 2020 15:18:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

HAOUAS Elyes (Code Review)

14 Sep 14 Sep

8:54 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Patrick Rudolph, Harshit Sharma,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42251

to look at the new patch set (#21).

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

crossgcc: Upgrade GCC to 10.2.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

Some changes: https://gcc.gnu.org/gcc-10/changes.html

Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.2.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-10.2.0_gnat.patch R util/crossgcc/patches/gcc-10.2.0_libcpp.patch R util/crossgcc/patches/gcc-10.2.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.2.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 11 files changed, 33 insertions(+), 21,484 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/21

HAOUAS Elyes (Code Review)

10:54 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Patrick Rudolph, Harshit Sharma,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42251

to look at the new patch set (#22).

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

crossgcc: Upgrade GCC to 10.2.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

Some changes: https://gcc.gnu.org/gcc-10/changes.html

Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.2.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-10.2.0_gnat.patch R util/crossgcc/patches/gcc-10.2.0_libcpp.patch R util/crossgcc/patches/gcc-10.2.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.2.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 11 files changed, 20 insertions(+), 21,475 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/22

HAOUAS Elyes (Code Review)

12:23 p.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Patrick Rudolph, Harshit Sharma,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42251

to look at the new patch set (#23).

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

crossgcc: Upgrade GCC to 10.2.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

Some changes: https://gcc.gnu.org/gcc-10/changes.html

Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.2.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-10.2.0_gnat.patch R util/crossgcc/patches/gcc-10.2.0_libcpp.patch R util/crossgcc/patches/gcc-10.2.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.2.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 11 files changed, 32 insertions(+), 21,487 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/23

Paul Menzel (Code Review)

29 Sep 29 Sep

10:01 p.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 23:

libpayload payloads like *coreinfo* do not build for me anymore with GCC 10.2.0. It works with GCC 9.3.0 for example.

``` $ cd payloads/coreinfo $ make olddefconfig $ make -j4 […] LPCC build/coreinfo.elf (LINK) /dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(exception.libc.o):/dev/shm/coreboot/payloads/libpayload/include/x86/arch/exception.h:64: multiple definition of `__packed'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(main.libc.o):/dev/shm/coreboot/payloads/libpayload/include/x86/arch/exception.h:64: first defined here /dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:153: multiple definition of `HcInterruptStatusReg'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:153: first defined here /dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:142: multiple definition of `HcFmRemainingReg'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:142: first defined here /dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:137: multiple definition of `HcCommandStatusMask'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:137: first defined here /dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:133: multiple definition of `HcCommandStatusReg'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:133: first defined here /dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:118: multiple definition of `HcControlMask'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:118: first defined here […] ```

-- To view, visit https://review.coreboot.org/c/coreboot/+/42251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Gerrit-Change-Number: 42251 Gerrit-PatchSet: 23 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Harshit Sharma harshitsharmajs@gmail.com Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: KOUAM Ledoux kouamdoux@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Tue, 29 Sep 2020 22:01:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

HAOUAS Elyes (Code Review)

30 Sep 30 Sep

6:54 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 23:

...

Patch Set 23:

libpayload payloads like *coreinfo* do not build for me anymore with GCC 10.2.0. It works with GCC 9.3.0 for example.

$ cd payloads/coreinfo
$ make olddefconfig
$ make -j4
[…]
    LPCC       build/coreinfo.elf (LINK)
/dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(exception.libc.o):/dev/shm/coreboot/payloads/libpayload/include/x86/arch/exception.h:64: multiple definition of `__packed'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(main.libc.o):/dev/shm/coreboot/payloads/libpayload/include/x86/arch/exception.h:64: first defined here
/dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:153: multiple definition of `HcInterruptStatusReg'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:153: first defined here
/dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:142: multiple definition of `HcFmRemainingReg'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:142: first defined here
/dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:137: multiple definition of `HcCommandStatusMask'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:137: first defined here
/dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:133: multiple definition of `HcCommandStatusReg'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:133: first defined here
/dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:118: multiple definition of `HcControlMask'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:118: first defined here
[…]

"/coreboot/payloads/libpayload/include/x86/arch/exception.h:64: multiple definition of `__packed'; " this is because "-fcommon" option changed to "-fno-common" in GCC10 ( https://gcc.gnu.org/gcc-10/porting_to.html ) "__attribute__((__packed__))" may fix that error.

for the others, I have no idea

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HAOUAS Elyes (Code Review)

7:07 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 23:

...

Patch Set 23:

...

Patch Set 23:

libpayload payloads like *coreinfo* do not build for me anymore with GCC 10.2.0. It works with GCC 9.3.0 for example.

$ cd payloads/coreinfo
$ make olddefconfig
$ make -j4
[…]
    LPCC       build/coreinfo.elf (LINK)
/dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(exception.libc.o):/dev/shm/coreboot/payloads/libpayload/include/x86/arch/exception.h:64: multiple definition of `__packed'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(main.libc.o):/dev/shm/coreboot/payloads/libpayload/include/x86/arch/exception.h:64: first defined here
/dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:153: multiple definition of `HcInterruptStatusReg'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:153: first defined here
/dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:142: multiple definition of `HcFmRemainingReg'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:142: first defined here
/dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:137: multiple definition of `HcCommandStatusMask'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:137: first defined here
/dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:133: multiple definition of `HcCommandStatusReg'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:133: first defined here
/dev/shm/coreboot/util/crossgcc/xgcc/lib/gcc/i386-elf/10.2.0/../../../../i386-elf/bin/ld: /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci_rh.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:118: multiple definition of `HcControlMask'; /dev/shm/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(ohci.libc.o):/dev/shm/coreboot/payloads/libpayload/drivers/usb/ohci_private.h:118: first defined here
[…]

for the others, I have no idea

maybe use "extern enum" for 'HcInterruptStatusReg' (and the others).

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Jacob Garber (Code Review)

24 Nov 24 Nov

2:46 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Jacob Garber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 23:

...

Patch Set 23:

libpayload payloads like *coreinfo* do not build for me anymore with GCC 10.2.0. It works with GCC 9.3.0 for example.

Those are fixed in CB:47153 and CB:47224. Now that 4.13 has been released, are there any other blockers for merging this?

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HAOUAS Elyes (Code Review)

7:05 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 23:

...

Patch Set 23:

...
Patch Set 23:

libpayload payloads like *coreinfo* do not build for me anymore with GCC 10.2.0. It works with GCC 9.3.0 for example.

Those are fixed in CB:47153 and CB:47224. Now that 4.13 has been released, are there any other blockers for merging this?

Bcz an overflow error.

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HAOUAS Elyes (Code Review)

8:26 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 24:

...

Patch Set 23:

...
Patch Set 23:

...
Patch Set 23:

libpayload payloads like *coreinfo* do not build for me anymore with GCC 10.2.0. It works with GCC 9.3.0 for example.

Those are fixed in CB:47153 and CB:47224. Now that 4.13 has been released, are there any other blockers for merging this?

Bcz an overflow error.

see https://qa.coreboot.org/job/coreboot-toolchain/945/testReport/junit/(root)/b...

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HAOUAS Elyes (Code Review)

8:29 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 25:

This rebase is my latest contribution. Please feel free to edit any of "my" changes ...

Thx @ all

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Nico Huber (Code Review)

5 p.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 25:

...

...
libpayload payloads like *coreinfo* do not build for me anymore with GCC 10.2.0. It works with GCC 9.3.0 for example.

Those are fixed in CB:47153 and CB:47224. Now that 4.13 has been released, are there any other blockers for merging this?

The questions that stopped me submitting this in August:

...

LGTM. Can we confirm that

a) the upstream NDS32 ITE support is sufficient, and

Stefan, Martin, Patrick, can we get this tested for chrome stuff? In case that is needed.

...

b) the FIT loader on ARM is indeed working (with patched `list.h`)?

Anybody?

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Stefan Reinauer (Code Review)

7:03 p.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 25: Code-Review+2

Looks good to me, but I can't speak for Chrome OS.

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Jacob Garber (Code Review)

25 Nov 25 Nov

4:55 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Jacob Garber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 25: Code-Review+1

...

...
b) the FIT loader on ARM is indeed working (with patched `list.h`)?

Anybody?

It looks like that was tested as part of CB:44573 (though Patrick can correct me if I'm wrong).

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Hung-Te Lin (Code Review)

23 Dec 23 Dec

3:38 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 25:

I'm not confident in merging this - can you rebase to latest head and let buildbot try again?

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HAOUAS Elyes (Code Review)

25 Dec 25 Dec

4:11 p.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Patch Set 26:

(8 comments)

Merry Christmas

current patch needs #46281 to build.

https://review.coreboot.org/c/coreboot/+/42251/26/util/crossgcc/buildgcc File util/crossgcc/buildgcc:

https://review.coreboot.org/c/coreboot/+/42251/26/util/crossgcc/buildgcc@36 PS26, Line 36: 6.2.0 old version

https://review.coreboot.org/c/coreboot/+/42251/26/util/crossgcc/buildgcc@38 PS26, Line 38: 1.2.0 old version

https://review.coreboot.org/c/coreboot/+/42251/26/util/crossgcc/buildgcc@40 PS26, Line 40: GCC_AUTOCONF_VERSION=2.69 not used at all ...

https://review.coreboot.org/c/coreboot/+/42251/26/util/crossgcc/buildgcc@42 PS26, Line 42: 9.2 old version

https://review.coreboot.org/c/coreboot/+/42251/26/util/crossgcc/buildgcc@43 PS26, Line 43: 20200925 old version

https://review.coreboot.org/c/coreboot/+/42251/26/util/crossgcc/buildgcc@44 PS26, Line 44: 3.8.5 old version

https://review.coreboot.org/c/coreboot/+/42251/26/util/crossgcc/buildgcc@45 PS26, Line 45: EXPAT_VERSION=2.2.9 old version

https://review.coreboot.org/c/coreboot/+/42251/26/util/crossgcc/buildgcc@48 PS26, Line 48: CMAKE_VERSION=3.18.1 old version

-- To view, visit https://review.coreboot.org/c/coreboot/+/42251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Gerrit-Change-Number: 42251 Gerrit-PatchSet: 26 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Harshit Sharma harshitsharmajs@gmail.com Gerrit-Reviewer: Jacob Garber jgarber1@ualberta.ca Gerrit-Reviewer: Julius Werner jwerner@chromium.org Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Stefan Reinauer stefan.reinauer@coreboot.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Hung-Te Lin hungte@chromium.org Gerrit-CC: KOUAM Ledoux kouamdoux@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 25 Dec 2020 16:11:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

HAOUAS Elyes (Code Review)

16 Jan 16 Jan

9:45 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Hello build bot (Jenkins), Nico Huber, Martin Roth, Patrick Georgi, Stefan Reinauer, Julius Werner, Jacob Garber, Patrick Rudolph, Harshit Sharma,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42251

to look at the new patch set (#27).

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

crossgcc: Upgrade GCC to 10.2.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

Some changes: https://gcc.gnu.org/gcc-10/changes.html

Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.2.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-10.2.0_gnat.patch R util/crossgcc/patches/gcc-10.2.0_libcpp.patch R util/crossgcc/patches/gcc-10.2.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.2.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 11 files changed, 33 insertions(+), 21,488 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/27

-- To view, visit https://review.coreboot.org/c/coreboot/+/42251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Gerrit-Change-Number: 42251 Gerrit-PatchSet: 27 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Harshit Sharma harshitsharmajs@gmail.com Gerrit-Reviewer: Jacob Garber jgarber1@ualberta.ca Gerrit-Reviewer: Julius Werner jwerner@chromium.org Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Stefan Reinauer stefan.reinauer@coreboot.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Hung-Te Lin hungte@chromium.org Gerrit-CC: KOUAM Ledoux kouamdoux@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

HAOUAS Elyes (Code Review)

9:50 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Hello build bot (Jenkins), Nico Huber, Martin Roth, Patrick Georgi, Stefan Reinauer, Julius Werner, Jacob Garber, Patrick Rudolph, Harshit Sharma,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42251

to look at the new patch set (#28).

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

crossgcc: Upgrade GCC to 10.2.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

Some changes: https://gcc.gnu.org/gcc-10/changes.html

Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.2.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-10.2.0_gnat.patch R util/crossgcc/patches/gcc-10.2.0_libcpp.patch R util/crossgcc/patches/gcc-10.2.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.2.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 11 files changed, 33 insertions(+), 21,488 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/28

-- To view, visit https://review.coreboot.org/c/coreboot/+/42251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Gerrit-Change-Number: 42251 Gerrit-PatchSet: 28 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Harshit Sharma harshitsharmajs@gmail.com Gerrit-Reviewer: Jacob Garber jgarber1@ualberta.ca Gerrit-Reviewer: Julius Werner jwerner@chromium.org Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Stefan Reinauer stefan.reinauer@coreboot.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Hung-Te Lin hungte@chromium.org Gerrit-CC: KOUAM Ledoux kouamdoux@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

HAOUAS Elyes (Code Review)

17 Jan 17 Jan

6:41 a.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

Attention is currently required from: HAOUAS Elyes. Hello build bot (Jenkins), Nico Huber, Martin Roth, Patrick Georgi, Stefan Reinauer, Julius Werner, Jacob Garber, Patrick Rudolph, Harshit Sharma,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42251

to look at the new patch set (#30).

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

crossgcc: Upgrade GCC to 10.2.0

nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore.

Some changes: https://gcc.gnu.org/gcc-10/changes.html

Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.2.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-10.2.0_gnat.patch R util/crossgcc/patches/gcc-10.2.0_libcpp.patch R util/crossgcc/patches/gcc-10.2.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.2.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 11 files changed, 32 insertions(+), 21,487 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/30

-- To view, visit https://review.coreboot.org/c/coreboot/+/42251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Gerrit-Change-Number: 42251 Gerrit-PatchSet: 30 Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Harshit Sharma harshitsharmajs@gmail.com Gerrit-Reviewer: Jacob Garber jgarber1@ualberta.ca Gerrit-Reviewer: Julius Werner jwerner@chromium.org Gerrit-Reviewer: Martin Roth martinroth@google.com Gerrit-Reviewer: Nico Huber nico.h@gmx.de Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Stefan Reinauer stefan.reinauer@coreboot.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Hung-Te Lin hungte@chromium.org Gerrit-CC: KOUAM Ledoux kouamdoux@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Attention: HAOUAS Elyes ehaouas@noos.fr Gerrit-MessageType: newpatchset

HAOUAS Elyes (Code Review)

17 Feb 17 Feb

6:27 p.m.

New subject: Change in coreboot[master]: crossgcc: Upgrade GCC to 10.2.0

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42251 )

Change subject: crossgcc: Upgrade GCC to 10.2.0 ......................................................................

Abandoned

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participants (9)

HAOUAS Elyes (Code Review)
Harshit Sharma (Code Review)
Hung-Te Lin (Code Review)
Jacob Garber (Code Review)
KOUAM Ledoux (Code Review)
Nico Huber (Code Review)
Patrick Georgi (Code Review)
Paul Menzel (Code Review)
Stefan Reinauer (Code Review)