Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges - coreboot-gerrit

9 Nov 2018


      Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29549 )
Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
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Patch Set 5: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608
Gerrit-Change-Number: 29549
Gerrit-PatchSet: 5
Gerrit-Owner: Mario Scheithauer mario.scheithauer@siemens.com
Gerrit-Reviewer: Mario Scheithauer mario.scheithauer@siemens.com
Gerrit-Reviewer: Werner Zeh werner.zeh@siemens.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Fri, 09 Nov 2018 08:30:58 +0000
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