[XS] Change in coreboot[main]: soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree

[Michał Kopeć (Code Review)]

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82685?usp=email )

Change subject: soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
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soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree

The comment that the PchHdaAudioLink UPDs only configure GPIOs is
incorrect. Setting this to 1 is needed to enable HDA audio link.

Same exact situation as with Alder Lake in CL 71715.

Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0
Signed-off-by: Michał Kopeć 
---
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 2 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/82685/1

diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index 0c76b7c..7168369 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -247,6 +247,7 @@
    uint16_t sata_ports_dito_val[8];

/* Audio related */
+	uint8_t pch_hda_audio_link_hda_enable;
    uint8_t pch_hda_dsp_enable;

bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS];
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index caf57a3..2bfaed1 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -288,17 +288,11 @@
    m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode;
    m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency;
    m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
+	m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_audio_link_hda_enable;

for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++)
    	m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i];

-	/*
-	 * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
-	 * configure GPIO pads for audio. Mainboard is expected to perform all GPIO
-	 * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO
-	 * configuration for audio pads.
-	 */
-	m_cfg->PchHdaAudioLinkHdaEnable = 0;
    memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
    memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
    memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));