Raymond Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: /mb/google/hatch: Create nightfury variant ......................................................................
/mb/google/hatch: Create nightfury variant
Create new variant for nightfury
BUG=b:149226871 TEST=emerge-hatch coreboot chromeos-bootimage and boot on nightfury proto board
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: raymondchung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 506 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 783ec73..26e96a2 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -98,6 +98,7 @@ default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU + default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index e216135..1ec4e87 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -43,6 +43,11 @@ select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384
+config BOARD_GOOGLE_NIGHTFURY + bool "-> Nightfury" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + config BOARD_GOOGLE_PUFF bool "-> Puff" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc new file mode 100644 index 0000000..c57d090 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc @@ -0,0 +1,28 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES += 8G_3200 # 0b110 +SPD_SOURCES += 16G_3200 # 0b111 +SPD_SOURCES += 16G_2666_2bg # 0b1000 +SPD_SOURCES += 16G_3200_4bg # 0b1001 + +bootblock-y += gpio.c +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c new file mode 100644 index 0000000..2bf97b1 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* C12 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_C12, 0, DEEP), + /* C15 : WWAN_DPR_SAR_ODL + * + * TODO: Driver doesn't use this pin as of now. In case driver starts + * using this pin, expose this pin to driver. + */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : EMMC_DATA0 ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : EMMC_DATA1 ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : EMMC_DATA2 ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : EMMC_DATA3 ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : EMMC_DATA4 ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : EMMC_DATA5 ==> NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : EMMC_DATA6 ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : EMMC_DATA7 ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EMMC_RCLK ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EMMC_CLK ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : EMMC_RESET# ==> NC */ + PAD_NC(GPP_F22, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See commit c41b0e8ea3b2714bf6d6d88a6b66c333c6919f07. + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as default_sleep_gpio_table + * but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..ffa7590 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 70 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 70 +#define DPTF_CPU_ACTIVE_AC1 65 +#define DPTF_CPU_ACTIVE_AC2 60 +#define DPTF_CPU_ACTIVE_AC3 50 +#define DPTF_CPU_ACTIVE_AC4 40 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 62 +#define DPTF_TSR0_CRITICAL 105 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 54 +#define DPTF_TSR1_CRITICAL 105 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 12000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 51000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h new file mode 100644 index 0000000..768987d --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h new file mode 100644 index 0000000..92f9d41 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +#endif diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb new file mode 100644 index 0000000..f3f6c3b --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -0,0 +1,177 @@ +chip soc/intel/cannonlake + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "51" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # VR Slew rate setting + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "FastPkgCRampDisableIa" = "1" + register "FastPkgCRampDisableGt" = "1" + register "FastPkgCRampDisableSa" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + register "probed" = "1" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_off_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "130" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" + device spi 1 on end + end # FPMCU + end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA + end + +end diff --git a/src/mainboard/google/hatch/variants/nightfury/ramstage.c b/src/mainboard/google/hatch/variants/nightfury/ramstage.c new file mode 100644 index 0000000..9b919fc --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +}
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: /mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38826/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38826/1//COMMIT_MSG@2 PS1, Line 2: raymondchung Please use *Raymond Chung*.
https://review.coreboot.org/c/coreboot/+/38826/1//COMMIT_MSG@7 PS1, Line 7: /mb/google/hatch: Create nightfury variant Please remove the leading /.
https://review.coreboot.org/c/coreboot/+/38826/1//COMMIT_MSG@9 PS1, Line 9: Create new variant for nightfury How did you create the variant?
https://review.coreboot.org/c/coreboot/+/38826/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/nightfury/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38826/1/src/mainboard/google/hatch/... PS1, Line 27: Kohaku Is that name correct?
Hello Tim Wawrzynczak, Philip Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#2).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant for nightfury
BUG=b:149226871 TEST=emerge-hatch coreboot chromeos-bootimage and boot on nightfury proto board
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 506 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/2
Hello Tim Wawrzynczak, Philip Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#3).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant for nightfury
BUG=b:149226871 TEST=emerge-hatch coreboot chromeos-bootimage and boot on nightfury proto board
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 507 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/3
Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38826/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38826/1//COMMIT_MSG@2 PS1, Line 2: raymondchung
Please use *Raymond Chung*.
ok
https://review.coreboot.org/c/coreboot/+/38826/1//COMMIT_MSG@7 PS1, Line 7: /mb/google/hatch: Create nightfury variant
Please remove the leading /.
ok
https://review.coreboot.org/c/coreboot/+/38826/1//COMMIT_MSG@9 PS1, Line 9: Create new variant for nightfury
How did you create the variant?
According to the needs of issue 149226871. We refer to CLs of jinlon to create new variant.
https://review.coreboot.org/c/coreboot/+/38826/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/nightfury/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38826/1/src/mainboard/google/hatch/... PS1, Line 27: Kohaku
Is that name correct?
Sorry! It is not correct. The correct name is nightfury.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38826/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38826/3//COMMIT_MSG@9 PS3, Line 9: Create new variant for nightfury missing a period at the end.
https://review.coreboot.org/c/coreboot/+/38826/3/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/nightfury/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38826/3/src/mainboard/google/hatch/... PS3, Line 7: : [PchSerialIoIndexI2C2] = PchSerialIoPci, : [PchSerialIoIndexI2C3] = PchSerialIoPci, Shouldn't these be disabled?
https://review.coreboot.org/c/coreboot/+/38826/3/src/mainboard/google/hatch/... PS3, Line 11: [PchSerialIoIndexI2C5] = PchSerialIoPci, And this one as well?
https://review.coreboot.org/c/coreboot/+/38826/3/src/mainboard/google/hatch/... PS3, Line 53: .i2c[3] = { : .speed = I2C_SPEED_FAST, : }, It's disabled in the devicetree
Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 3: Code-Review+1
LGTM pending resolution of the other review comments.
Hello Bob Moragues, Tim Wawrzynczak, Philip Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#4).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant for nightfury.
BUG=b:149226871 TEST=emerge-hatch coreboot chromeos-bootimage and boot on nightfury proto board
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 507 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/4
Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 4:
(4 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/38826/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38826/3//COMMIT_MSG@9 PS3, Line 9: Create new variant for nightfury
missing a period at the end.
Done
https://review.coreboot.org/c/coreboot/+/38826/3/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/nightfury/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38826/3/src/mainboard/google/hatch/... PS3, Line 7: : [PchSerialIoIndexI2C2] = PchSerialIoPci, : [PchSerialIoIndexI2C3] = PchSerialIoPci,
Shouldn't these be disabled?
I think it is another CML-based Samsung device, which is a better reference in this case.
https://review.coreboot.org/c/coreboot/+/38826/3/src/mainboard/google/hatch/... PS3, Line 11: [PchSerialIoIndexI2C5] = PchSerialIoPci,
And this one as well?
I think it is another CML-based Samsung device, which is a better reference in this case.
https://review.coreboot.org/c/coreboot/+/38826/3/src/mainboard/google/hatch/... PS3, Line 53: .i2c[3] = { : .speed = I2C_SPEED_FAST, : },
It's disabled in the devicetree
I think it is another CML-based Samsung device, which is a better reference in this case.
Hello Bob Moragues, Tim Wawrzynczak, Philip Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#5).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant for nightfury.
BUG=b:149226871 TEST=emerge-hatch coreboot chromeos-bootimage and boot on nightfury proto board
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 507 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/5
Hello Bob Moragues, Tim Wawrzynczak, Philip Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#6).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST=emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 507 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/6
Hello Bob Moragues, Tim Wawrzynczak, Philip Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#7).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 BRANCH=None TEST=emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 507 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/7
Hello Bob Moragues, Tim Wawrzynczak, Philip Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#8).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 507 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/8
Hello Bob Moragues, Tim Wawrzynczak, Philip Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#9).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST='FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage'
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 507 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/9
Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 10: Code-Review+1
(6 comments)
Please correct the copyrights
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 3: 2019 2020
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/gpio.c:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019 2020
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019 2020
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019 2020
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019 2020
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019 2020
Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 10:
Patch Set 10: Code-Review+1
(6 comments)
Please correct the copyrights
We have modified this.
Hello Bob Moragues, Tim Wawrzynczak, Philip Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#11).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST='FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage'
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 507 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/11
Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 15:
This change is ready for review.
Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 15: Code-Review+1
(6 comments)
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 3: 2019
2020
Done
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/gpio.c:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019
2020
Done
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019
2020
Done
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019
2020
Done
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019
2020
Done
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019
2020
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38826/15/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38826/15/src/mainboard/google/hatch... PS15, Line 53: .i2c[3] = { : .speed = I2C_SPEED_FAST, : }, This device is turned off below.
Hello Bob Moragues, Tim Wawrzynczak, Philip Chen, Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#16).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST='FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage'
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 504 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/16
Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 17:
(1 comment)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/38826/15/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38826/15/src/mainboard/google/hatch... PS15, Line 53: .i2c[3] = { : .speed = I2C_SPEED_FAST, : },
This device is turned off below.
Done
Hello Bob Moragues, Tim Wawrzynczak, Philip Chen, Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#18).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 9 files changed, 504 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/18
Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 18: Code-Review+1
Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 23:
This change is ready for review.
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38826/24/src/mainboard/google/hatch... File src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex:
https://review.coreboot.org/c/coreboot/+/38826/24/src/mainboard/google/hatch... PS24, Line 1: 24 20 0F 0E 15 19 01 08 00 00 00 0B 03 03 00 00 Please pull out the new SPD file and put this in a separate CL
Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 29:
(1 comment)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/38826/24/src/mainboard/google/hatch... File src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex:
https://review.coreboot.org/c/coreboot/+/38826/24/src/mainboard/google/hatch... PS24, Line 1: 24 20 0F 0E 15 19 01 08 00 00 00 0B 03 03 00 00
Please pull out the new SPD file and put this in a separate CL
Done
Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Philip Chen, Bob Moragues, Bob Moragues, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#32).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/memory.c A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 10 files changed, 758 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/32
Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Philip Chen, Bob Moragues, Bob Moragues, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#33).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/memory.c A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 10 files changed, 758 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/33
Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Philip Chen, Bob Moragues, Bob Moragues, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#34).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/memory.c A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 10 files changed, 758 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/34
Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 38:
Patch Set 29:
(1 comment)
This change is ready for review.
Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 38: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/memory.c:
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... PS38, Line 4: (C) Does this (C) conform to the template?
Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 38:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/memory.c:
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... PS38, Line 4: 2018 Actually it's 2020.
Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Philip Chen, Bob Moragues, Bob Moragues, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#39).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/memory.c A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 10 files changed, 757 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/39
Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 40:
(2 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/memory.c:
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... PS38, Line 4: 2018
Actually it's 2020.
Done
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... PS38, Line 4: (C)
Does this (C) conform to the template?
I'm not sure. This is a copy from the kohaku variant. But we can modify it.
Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 40:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/memory.c:
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... PS38, Line 4: 2018
Done
Done
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... PS38, Line 4: (C)
I'm not sure. This is a copy from the kohaku variant. But we can modify it.
Done
Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 40:
Hi Raymond, could you stack this CL on top of CL:39271? Otherwise this CL doesn't compile (verified -1).
Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Philip Chen, Bob Moragues, Bob Moragues, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#41).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/memory.c A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 10 files changed, 758 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/41
Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 43:
This change is ready for review.
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 43:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38826/43/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38826/43/src/mainboard/google/hatch... PS43, Line 29: gpio_output(GPP_C11, 1); : mdelay(1); : gpio_output(GPP_A12, 1); This is specific to the FPMCU. I didn't find one when looking through the schematics -- do you have one? If not, you should remove these. Additionally, make sure you NC (or configure them apprpriately if they're being used for something else) the FPMCU gpios in gpio.c. Quick search through baseboard shows that to be GPP_A21, GPP_A23, GPP_B20-GPP_B23, GPP_C11.
SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 43:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38826/43/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38826/43/src/mainboard/google/hatch... PS43, Line 29: gpio_output(GPP_C11, 1); : mdelay(1); : gpio_output(GPP_A12, 1);
This is specific to the FPMCU. […]
1. This code can be removed. 2. As I checked unused GPIO pads in current schematics have been configured as NC now.
Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Philip Chen, Bob Moragues, Bob Moragues, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38826
to look at the new patch set (#44).
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/memory.c A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 10 files changed, 755 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/38826/44
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 44: Code-Review+2
Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 44:
Raymond, please click on 'resolve' for all pending comments. Thanks.
Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 44: Code-Review+1
(19 comments)
Patch Set 44:
Raymond, please click on 'resolve' for all pending comments. Thanks.
Hi Philip,
We have finished.
https://review.coreboot.org/c/coreboot/+/38826/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38826/1//COMMIT_MSG@2 PS1, Line 2: raymondchung
ok
Done
https://review.coreboot.org/c/coreboot/+/38826/1//COMMIT_MSG@7 PS1, Line 7: /mb/google/hatch: Create nightfury variant
ok
Done
https://review.coreboot.org/c/coreboot/+/38826/1//COMMIT_MSG@9 PS1, Line 9: Create new variant for nightfury
According to the needs of issue 149226871. […]
Done
https://review.coreboot.org/c/coreboot/+/38826/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38826/3//COMMIT_MSG@9 PS3, Line 9: Create new variant for nightfury
Done
Done
https://review.coreboot.org/c/coreboot/+/38826/24/src/mainboard/google/hatch... File src/mainboard/google/hatch/spd/LP_4G_2133.spd.hex:
https://review.coreboot.org/c/coreboot/+/38826/24/src/mainboard/google/hatch... PS24, Line 1: 24 20 0F 0E 15 19 01 08 00 00 00 0B 03 03 00 00
Done
Done
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 3: 2019
Done
Done
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/gpio.c:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019
Done
Done
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019
Done
Done
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019
Done
Done
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019
Done
Done
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/memory.c:
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... PS38, Line 4: 2018
Done
Done
https://review.coreboot.org/c/coreboot/+/38826/38/src/mainboard/google/hatch... PS38, Line 4: (C)
Done
Done
https://review.coreboot.org/c/coreboot/+/38826/3/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/nightfury/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38826/3/src/mainboard/google/hatch/... PS3, Line 7: : [PchSerialIoIndexI2C2] = PchSerialIoPci, : [PchSerialIoIndexI2C3] = PchSerialIoPci,
I think it is another CML-based Samsung device, which is a better reference in this case.
Done
https://review.coreboot.org/c/coreboot/+/38826/3/src/mainboard/google/hatch/... PS3, Line 11: [PchSerialIoIndexI2C5] = PchSerialIoPci,
I think it is another CML-based Samsung device, which is a better reference in this case.
Done
https://review.coreboot.org/c/coreboot/+/38826/3/src/mainboard/google/hatch/... PS3, Line 53: .i2c[3] = { : .speed = I2C_SPEED_FAST, : },
I think it is another CML-based Samsung device, which is a better reference in this case.
Done
https://review.coreboot.org/c/coreboot/+/38826/15/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38826/15/src/mainboard/google/hatch... PS15, Line 53: .i2c[3] = { : .speed = I2C_SPEED_FAST, : },
Done
Done
https://review.coreboot.org/c/coreboot/+/38826/1/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/nightfury/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38826/1/src/mainboard/google/hatch/... PS1, Line 27: Kohaku
Sorry! It is not correct. The correct name is nightfury.
Done
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38826/10/src/mainboard/google/hatch... PS10, Line 4: 2019
Done
Done
https://review.coreboot.org/c/coreboot/+/38826/43/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38826/43/src/mainboard/google/hatch... PS43, Line 29: gpio_output(GPP_C11, 1); : mdelay(1); : gpio_output(GPP_A12, 1);
- This code can be removed. […]
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
mb/google/hatch: Create nightfury variant
Create new variant and build for nightfury.
BUG=b:149226871 TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38826 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Shelley Chen shchen@google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/nightfury/Makefile.inc A src/mainboard/google/hatch/variants/nightfury/gpio.c A src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h A src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h A src/mainboard/google/hatch/variants/nightfury/memory.c A src/mainboard/google/hatch/variants/nightfury/overridetree.cb A src/mainboard/google/hatch/variants/nightfury/ramstage.c 10 files changed, 755 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved Raymond Chung: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 92d94db..b0d2e75 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -99,6 +99,7 @@ default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU + default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE
@@ -122,6 +123,7 @@ default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "mushu" if BOARD_GOOGLE_MUSHU + default "nightfury" if BOARD_GOOGLE_NIGHTFURY default "puff" if BOARD_GOOGLE_PUFF default "stryke" if BOARD_GOOGLE_STRYKE
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index fe1e334..785e2c8 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -44,6 +44,11 @@ select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384
+config BOARD_GOOGLE_NIGHTFURY + bool "-> Nightfury" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + config BOARD_GOOGLE_PUFF bool "-> Puff" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/nightfury/Makefile.inc b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc new file mode 100644 index 0000000..f46b7b0 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/Makefile.inc @@ -0,0 +1,24 @@ +## This file is part of the coreboot project. +## +## Copyright 2020 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = LP_8G_2133 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += LP_4G_2133 # 0b010 + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c new file mode 100644 index 0000000..681f9ec --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -0,0 +1,178 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* A18 : NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : NC */ + PAD_NC(GPP_A20, NONE), + /* A22 : NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : NC */ + PAD_NC(GPP_A23, NONE), + + /* B8 : NC */ + PAD_NC(GPP_B8, NONE), + /* B20 : NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : NC */ + PAD_NC(GPP_B22, NONE), + + /* C1 : NC */ + PAD_NC(GPP_C1, NONE), + /* C12 : EN_PP3300_TSP_DX */ + PAD_CFG_GPO(GPP_C12, 0, DEEP), + /* C13 : EC_PCH_INT_L - needs to wake the system */ + PAD_CFG_GPI_IRQ_WAKE(GPP_C13, NONE, PLTRST, LEVEL, INVERT), + /* C23 : UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + + /* D16 : TOUCHSCREEN_INT_L */ + PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), + + /* E4 : M2_SSD_PE_WAKE_ODL ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + + /* F1 : GPP_F1 ==> NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H4 : NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : NC */ + PAD_NC(GPP_H5, NONE), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + /* F3 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* H19 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See https://review.coreboot.org/c/coreboot/+/32111 . + */ +static const struct pad_config default_sleep_gpio_table[] = { + +}; + +/* + * GPIO settings before entering S5, which are same as + * default_sleep_gpio_table but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..edfad4b --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/acpi/dptf.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 50 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor - Charger" +#define DPTF_TSR0_PASSIVE 45 +#define DPTF_TSR0_CRITICAL 90 +#define DPTF_TSR0_TABLET_PASSIVE 32 +#define DPTF_TSR0_TABLET_CRITICAL 90 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor - 5V" +#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_CRITICAL 90 +#define DPTF_TSR1_TABLET_PASSIVE 32 +#define DPTF_TSR1_TABLET_CRITICAL 90 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - IA" +#define DPTF_TSR2_PASSIVE 45 +#define DPTF_TSR2_CRITICAL 90 +#define DPTF_TSR2_TABLET_PASSIVE 32 +#define DPTF_TSR2_TABLET_CRITICAL 90 + +#define DPTF_TSR3_SENSOR_ID 3 +#define DPTF_TSR3_SENSOR_NAME "Thermal Sensor - GT" +#define DPTF_TSR3_PASSIVE 45 +#define DPTF_TSR3_CRITICAL 90 +#define DPTF_TSR3_TABLET_PASSIVE 32 +#define DPTF_TSR3_TABLET_CRITICAL 90 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on 5V (TSR1) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR1, 100, 10, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR0) */ + Package () { _SB.DPTF.TCHG, _SB.DPTF.TSR0, 100, 94, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on IA (TSR2) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on GT (TSR3) */ + Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR3, 100, 10, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 7000, /* PowerLimitMinimum */ + 9000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 250 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 51000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h new file mode 100644 index 0000000..5b321a3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/ec.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#define EC_ENABLE_MULTIPLE_DPTF_PROFILES + +/* Add EC_HOST_EVENT_MKBP from baseboard */ +#undef MAINBOARD_EC_S3_WAKE_EVENTS +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +/* Removing EC_HOST_EVENT_MKBP from baseboard mask */ +#undef MAINBOARD_EC_SCI_EVENTS +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#endif /* VARIANT_EC_H */ diff --git a/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h new file mode 100644 index 0000000..2193c7b --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +#endif diff --git a/src/mainboard/google/hatch/variants/nightfury/memory.c b/src/mainboard/google/hatch/variants/nightfury/memory.c new file mode 100644 index 0000000..7e1594c --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/memory.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <soc/cnl_memcfg_init.h> +#include <string.h> + +static const struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the SoC pins to the lpddr3 pins + * for both channels. + * + * "The index of the array is CPU byte number, the values are DRAM byte + * numbers." - doc #573387 + * + * the index = pin number on SoC + * the value = pin number on lpddr3 part + */ + .dqs_map[DDR_CH0] = {0, 1, 3, 2, 5, 7, 6, 4}, + .dqs_map[DDR_CH1] = {1, 3, 2, 0, 5, 7, 6, 4}, + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0x0, 0xf0}, + {0xf, 0xf0}, + {0xf, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0x0, 0xf0}, + {0xf, 0xf0}, + {0xf, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + + /* Nightfury uses 200, 80.6 and 162 rcomp resistors */ + .rcomp_resistor = {200, 81, 162}, + + /* Nightfury Rcomp target values */ + .rcomp_targets = {100, 40, 40, 23, 40}, + + /* Set CaVref config to 0 for LPDDR3 */ + .vref_ca_config = 0, + + /* Disable Early Command Training */ + .ect = 0, +}; + +void variant_memory_params(struct cnl_mb_cfg *bcfg) +{ + memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); +} diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb new file mode 100644 index 0000000..0cf18e7 --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -0,0 +1,281 @@ +chip soc/intel/cannonlake + register "tdp_pl1_override" = "8" + register "tdp_pl2_override" = "51" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # No PCIe WiFi + register "PcieRpEnable[13]" = "0" + + # Enable DMIC1 + register "PchHdaAudioLinkDmic1" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb3_ports[3]" = "USB3_PORT_EMPTY" + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | Digitizer | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 135, + .fall_time_ns = 45, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 95, + .fall_time_ns = 55, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-14.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-14.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-14.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-14.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-14.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-14.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + device usb 2.2 off end + end + chip drivers/usb/acpi + device usb 2.3 off end + end + chip drivers/usb/acpi + device usb 2.4 off end + end + chip drivers/usb/acpi + device usb 2.5 off end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + device usb 2.7 off end + end + chip drivers/usb/acpi + device usb 2.8 off end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + device usb 3.2 off end + end + chip drivers/usb/acpi + device usb 3.3 off end + end + chip drivers/usb/acpi + device usb 3.4 off end + end + end + end + end + + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "generic.probed" = "1" + register "generic.wake" = "GPE0_DW0_21" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x20 on end + end + end # I2C 0 + + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""atmel,maxtouch"" + register "desc" = ""Atmel Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "91" # 90.5 ms + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" + register "enable_delay_ms" = "1" # 90 ns + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + register "probed" = "1" + device i2c 4b on end + end + + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "100" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "has_power_resource" = "1" + device i2c 10 on end + end + end # I2C #1 + + device pci 15.2 off end # I2C #2 + + device pci 19.0 on + chip drivers/i2c/da7219 + # TODO: these settings were copied from another board + # with the same chip. verify the settings + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 0x1a on end + end + end + + # No PCIe WiFi + device pci 1d.5 off end + device pci 1a.0 on end #eMMC + device pci 1e.3 off end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA + end # domain +end diff --git a/src/mainboard/google/hatch/variants/nightfury/ramstage.c b/src/mainboard/google/hatch/variants/nightfury/ramstage.c new file mode 100644 index 0000000..44cd89b --- /dev/null +++ b/src/mainboard/google/hatch/variants/nightfury/ramstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Nightfury. + */ +}
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38826 )
Change subject: mb/google/hatch: Create nightfury variant ......................................................................
Patch Set 45:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38826/45/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/nightfury/ramstage.c:
https://review.coreboot.org/c/coreboot/+/38826/45/src/mainboard/google/hatch... PS45, Line 23: /* : * Enable power to FPMCU, wait for power rail to stabilize, : * and then deassert FPMCU reset. : * Waiting for the power rail to stabilize can take a while, : * a minimum of 400us on Nightfury. : */ But there's no code here?