Change in ...coreboot[master]: nb/intel/sandybridge/acpi: Don't use defines for memory ranges

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Patrick Rudolph (Code Review)

27 Mar 2019 27 Mar '19

11:50 a.m.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32074

Change subject: nb/intel/sandybridge/acpi: Don't use defines for memory ranges ......................................................................

nb/intel/sandybridge/acpi: Don't use defines for memory ranges

Read the northbridge BARs from device PCI0:0.0.

Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl 2 files changed, 22 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32074/1

diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 09b8892..44fd36c 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -103,7 +103,7 @@ Name (CTCD, 1) /* CTDP Down Select */ Name (CTCU, 2) /* CTDP Up Select */

- OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) + OperationRegion (MCHB, SystemMemory, _SB.PCI0.MCHC.MHBR << 14, 0x8000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x5930), diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index dce9f67..93e0722 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -15,7 +15,6 @@ * GNU General Public License for more details. */

-#include "../sandybridge.h" #include "hostbridge.asl" #include "peg.asl"

@@ -27,12 +26,13 @@

Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) - Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) + // Filled by _CRS + Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) + Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) + Memory32Fixed(ReadWrite, 0, 0x00001000, EGPB) + Memory32Fixed(ReadWrite, 0, 0x04000000, PCIX) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH - Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

#if CONFIG(CHROMEOS_RAMOOPS) @@ -48,6 +48,21 @@ // Current Resource Settings Method (_CRS, 0, Serialized) { + CreateDwordField (PDRS, ^MCHB._BAS, MBR0) + MBR0 = _SB.PCI0.MCHC.MHBR << 14 + + CreateDwordField (PDRS, ^DMIB._BAS, DBR0) + DBR0 = _SB.PCI0.MCHC.DMBR << 13 + + CreateDwordField (PDRS, ^EGPB._BAS, EBR0) + EBR0 = _SB.PCI0.MCHC.DMBR << 12 + + CreateDwordField (PDRS, ^PCIX._BAS, XBR0) + XBR0 = _SB.PCI0.MCHC.PXBR << 26 + + CreateDwordField (PDRS, ^PCIX._LEN, XSZ0) + XSZ0 = 0x10000000 << _SB.PCI0.MCHC.PXSZ + Return(PDRS) } }

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Patrick Rudolph (Code Review)

3 Apr 3 Apr

7:22 a.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32074

to look at the new patch set (#5).

Change subject: nb/intel/sandybridge/acpi: Don't use defines for memory ranges ......................................................................

nb/intel/sandybridge/acpi: Don't use defines for memory ranges

Read the northbridge BARs from device PCI0:0.0.

Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32074/5

-- To view, visit https://review.coreboot.org/c/coreboot/+/32074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Gerrit-Change-Number: 32074 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Paul Menzel (Code Review)

12:41 p.m.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32074 )

Change subject: nb/intel/sandybridge/acpi: Don't use defines for memory ranges ......................................................................

Patch Set 5: Code-Review+1

-- To view, visit https://review.coreboot.org/c/coreboot/+/32074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Gerrit-Change-Number: 32074 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 03 Apr 2019 10:41:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

HAOUAS Elyes (Code Review)

1 May 1 May

9:26 a.m.

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32074 )

Change subject: nb/intel/sandybridge/acpi: Don't use defines for memory ranges ......................................................................

Patch Set 7: Code-Review+1

-- To view, visit https://review.coreboot.org/c/coreboot/+/32074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Gerrit-Change-Number: 32074 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 01 May 2019 07:26:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Felix Held (Code Review)

4 Jun 4 Jun

2:35 p.m.

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32074 )

Change subject: nb/intel/sandybridge/acpi: Don't use defines for memory ranges ......................................................................

Patch Set 7: Code-Review+1

-- To view, visit https://review.coreboot.org/c/coreboot/+/32074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Gerrit-Change-Number: 32074 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Tue, 04 Jun 2019 12:35:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Felix Held (Code Review)

7 Jun 7 Jun

3:44 p.m.

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32074 )

Change subject: nb/intel/sandybridge/acpi: Don't use defines for memory ranges ......................................................................

Patch Set 7: Code-Review-1

(9 comments)

https://review.coreboot.org/#/c/32074/7/src/northbridge/intel/sandybridge/ac... File src/northbridge/intel/sandybridge/acpi/hostbridge.asl:

https://review.coreboot.org/#/c/32074/7/src/northbridge/intel/sandybridge/ac... PS7, Line 34: 24 27

https://review.coreboot.org/#/c/32074/7/src/northbridge/intel/sandybridge/ac... PS7, Line 38: 13 14

https://review.coreboot.org/#/c/32074/7/src/northbridge/intel/sandybridge/ac... PS7, Line 39: 22 24

https://review.coreboot.org/#/c/32074/7/src/northbridge/intel/sandybridge/ac... PS7, Line 46: 10 11

https://review.coreboot.org/#/c/32074/7/src/northbridge/intel/sandybridge/ac... PS7, Line 51: 24 27

https://review.coreboot.org/#/c/32074/7/src/northbridge/intel/sandybridge/ac... PS7, Line 106: 14 15

https://review.coreboot.org/#/c/32074/7/src/northbridge/intel/sandybridge/ac... File src/northbridge/intel/sandybridge/acpi/sandybridge.asl:

https://review.coreboot.org/#/c/32074/7/src/northbridge/intel/sandybridge/ac... PS7, Line 52: 14 15

https://review.coreboot.org/#/c/32074/7/src/northbridge/intel/sandybridge/ac... PS7, Line 55: 13 12

https://review.coreboot.org/#/c/32074/7/src/northbridge/intel/sandybridge/ac... PS7, Line 58: DMBR is this correct? seems wrong to me, since it's just the last resource repeated. should this have been EPBR?

-- To view, visit https://review.coreboot.org/c/coreboot/+/32074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Gerrit-Change-Number: 32074 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Fri, 07 Jun 2019 13:44:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Patrick Rudolph (Code Review)

15 Jul 15 Jul

5:18 p.m.

New subject: Change in coreboot[master]: nb/intel/sandybridge/acpi: Don't use defines for memory ranges

Hello Patrick Rudolph, Felix Held, HAOUAS Elyes, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32074

to look at the new patch set (#8).

Change subject: nb/intel/sandybridge/acpi: Don't use defines for memory ranges ......................................................................

nb/intel/sandybridge/acpi: Don't use defines for memory ranges

Read the northbridge BARs from device PCI0:0.0.

Untested.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32074/8

-- To view, visit https://review.coreboot.org/c/coreboot/+/32074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Gerrit-Change-Number: 32074 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: newpatchset

Felix Held (Code Review)

5:51 p.m.

New subject: Change in coreboot[master]: nb/intel/sandybridge/acpi: Don't use defines for memory ranges

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32074 )

Change subject: nb/intel/sandybridge/acpi: Don't use defines for memory ranges ......................................................................

Patch Set 8: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/32074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Gerrit-Change-Number: 32074 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Mon, 15 Jul 2019 15:51:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Felix Held (Code Review)

18 Jul 18 Jul

3:51 p.m.

New subject: Change in coreboot[master]: nb/intel/sandybridge/acpi: Don't use defines for memory ranges

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32074 )

Change subject: nb/intel/sandybridge/acpi: Don't use defines for memory ranges ......................................................................

Patch Set 8:

(9 comments)

mark all fixed issues as done to be able to merge the patch

https://review.coreboot.org/c/coreboot/+/32074/7/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/acpi/hostbridge.asl:

https://review.coreboot.org/c/coreboot/+/32074/7/src/northbridge/intel/sandy... PS7, Line 34: 24

...

27

Done

https://review.coreboot.org/c/coreboot/+/32074/7/src/northbridge/intel/sandy... PS7, Line 38: 13

...

14

Done

https://review.coreboot.org/c/coreboot/+/32074/7/src/northbridge/intel/sandy... PS7, Line 39: 22

...

24

Done

https://review.coreboot.org/c/coreboot/+/32074/7/src/northbridge/intel/sandy... PS7, Line 46: 10

...

11

Done

https://review.coreboot.org/c/coreboot/+/32074/7/src/northbridge/intel/sandy... PS7, Line 51: 24

...

27

Done

https://review.coreboot.org/c/coreboot/+/32074/7/src/northbridge/intel/sandy... PS7, Line 106: 14

...

15

Done

https://review.coreboot.org/c/coreboot/+/32074/7/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/acpi/sandybridge.asl:

https://review.coreboot.org/c/coreboot/+/32074/7/src/northbridge/intel/sandy... PS7, Line 52: 14

...

15

Done

https://review.coreboot.org/c/coreboot/+/32074/7/src/northbridge/intel/sandy... PS7, Line 55: 13

...

12

Done

https://review.coreboot.org/c/coreboot/+/32074/7/src/northbridge/intel/sandy... PS7, Line 58: DMBR

...

is this correct? seems wrong to me, since it's just the last resource repeated. […]

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/32074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Gerrit-Change-Number: 32074 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Thu, 18 Jul 2019 13:51:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held felix-coreboot@felixheld.de Gerrit-MessageType: comment

Felix Held (Code Review)

3:52 p.m.

New subject: Change in coreboot[master]: nb/intel/sandybridge/acpi: Don't use defines for memory ranges

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32074 )

Change subject: nb/intel/sandybridge/acpi: Don't use defines for memory ranges ......................................................................

nb/intel/sandybridge/acpi: Don't use defines for memory ranges

Read the northbridge BARs from device PCI0:0.0.

Untested.

Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32074 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl 2 files changed, 27 insertions(+), 12 deletions(-)

Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved

diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 09b8892..4c4a509 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -31,24 +31,24 @@ Offset (0x40), // EPBAR EPEN, 1, // Enable , 11, // - EPBR, 24, // EPBAR + EPBR, 27, // EPBAR

Offset (0x48), // MCHBAR MHEN, 1, // Enable - , 13, // - MHBR, 22, // MCHBAR + , 14, // + MHBR, 24, // MCHBAR Offset (0x54), DVEN, 32, Offset (0x60), // PCIe BAR PXEN, 1, // Enable PXSZ, 2, // BAR size , 23, // - PXBR, 10, // PCIe BAR + PXBR, 13, // PCIe BAR

Offset (0x68), // DMIBAR DMEN, 1, // Enable , 11, // - DMBR, 24, // DMIBAR + DMBR, 27, // DMIBAR

Offset (0x70), // ME Base Address MEBA, 64, @@ -103,7 +103,7 @@ Name (CTCD, 1) /* CTDP Down Select */ Name (CTCU, 2) /* CTDP Up Select */

- OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) + OperationRegion (MCHB, SystemMemory, _SB.PCI0.MCHC.MHBR << 15, 0x8000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x5930), diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index dce9f67..7fdfe42 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -15,7 +15,6 @@ * GNU General Public License for more details. */

-#include "../sandybridge.h" #include "hostbridge.asl" #include "peg.asl"

@@ -27,12 +26,13 @@

#if CONFIG(CHROMEOS_RAMOOPS) @@ -48,6 +48,21 @@ // Current Resource Settings Method (_CRS, 0, Serialized) { + CreateDwordField (PDRS, ^MCHB._BAS, MBR0) + MBR0 = _SB.PCI0.MCHC.MHBR << 15 + + CreateDwordField (PDRS, ^DMIB._BAS, DBR0) + DBR0 = _SB.PCI0.MCHC.DMBR << 12 + + CreateDwordField (PDRS, ^EGPB._BAS, EBR0) + EBR0 = _SB.PCI0.MCHC.EPBR << 12 + + CreateDwordField (PDRS, ^PCIX._BAS, XBR0) + XBR0 = _SB.PCI0.MCHC.PXBR << 26 + + CreateDwordField (PDRS, ^PCIX._LEN, XSZ0) + XSZ0 = 0x10000000 << _SB.PCI0.MCHC.PXSZ + Return(PDRS) } }

-- To view, visit https://review.coreboot.org/c/coreboot/+/32074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Gerrit-Change-Number: 32074 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr Gerrit-Reviewer: Patrick Rudolph patrick.rudolph@9elements.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: merged

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Felix Held (Code Review)
HAOUAS Elyes (Code Review)
Patrick Rudolph (Code Review)
Paul Menzel (Code Review)