Change in ...coreboot[master]: mb/google/dragonegg: Override FSP default GPIO PM configuration
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32847
Change subject: mb/google/dragonegg: Override FSP default GPIO PM configuration ......................................................................
mb/google/dragonegg: Override FSP default GPIO PM configuration
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration GPIO_COMM_1: Disable RCOMP clock gating
Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/32847/1
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index 257ad1d..f820924 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -167,6 +167,16 @@ }, }"
+ # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device
Hello Aaron Durbin, Aamir Bohra, Rizwan Qureshi, V Sowmya, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32847
to look at the new patch set (#2).
Change subject: mb/google/dragonegg: Override FSP default GPIO PM configuration ......................................................................
mb/google/dragonegg: Override FSP default GPIO PM configuration
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration. GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D16 IRQ mapped for H1 TPM.
Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/32847/2
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32847 )
Change subject: mb/google/dragonegg: Override FSP default GPIO PM configuration ......................................................................
Patch Set 2: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32847 )
Change subject: mb/google/dragonegg: Override FSP default GPIO PM configuration ......................................................................
Patch Set 2: Code-Review+2
Hello Aaron Durbin, Aamir Bohra, Duncan Laurie, Rizwan Qureshi, V Sowmya, Lijian Zhao, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32847
to look at the new patch set (#3).
Change subject: mb/google/dragonegg: Override FSP default GPIO PM configuration ......................................................................
mb/google/dragonegg: Override FSP default GPIO PM configuration
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration. GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D16 IRQ mapped for H1 TPM.
BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media
Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/32847/3
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32847 )
Change subject: mb/google/dragonegg: Override FSP default GPIO PM configuration ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32847 )
Change subject: mb/google/dragonegg: Override FSP default GPIO PM configuration ......................................................................
mb/google/dragonegg: Override FSP default GPIO PM configuration
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration. GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D16 IRQ mapped for H1 TPM.
BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media
Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32847 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb 1 file changed, 10 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index 257ad1d..f820924 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -167,6 +167,16 @@ }, }"
+ # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device
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Aamir Bohra (Code Review) -
Furquan Shaikh (Code Review)
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Patrick Georgi (Code Review)
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Subrata Banik (Code Review)