Attention is currently required from: Jonathan Zhang, Christian Walter, Arthur Heymans, Tim Chu.
Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69143 )
Change subject: soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M ......................................................................
soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M
EWL (Enhanced Warning Log) is a FSP HOB generated by FSP-M that may contain several warnings/errors related to core, uncore and memory, etc.
mainboard can override it in its romstage.c for its own Enhanced Warning Log check.
Change-Id: I6f542e71d20307397c398fd757d9408438f681ed Signed-off-by: Johnny Lin johnny_lin@wiwynn.com --- M src/soc/intel/xeon_sp/include/soc/romstage.h M src/soc/intel/xeon_sp/romstage.c 2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/69143/1
diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index 90689af..a2adfed 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -9,4 +9,6 @@ void mainboard_memory_init_params(FSPM_UPD * mupd); void mainboard_rtc_failed(void); void save_dimm_info(void); +void mainboard_ewl_check(void); + #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index b1c7b3b..d001d61 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -15,6 +15,7 @@
fsp_memory_init(false); printk(BIOS_DEBUG, "coreboot fsp_memory_init finished...\n"); + mainboard_ewl_check();
unlock_pam_regions();
@@ -31,3 +32,4 @@
} __weak void save_dimm_info(void) { } +__weak void mainboard_ewl_check(void) { }