[S] Change in coreboot[master]: mb/intel/dcp847ske: Post-Haswell cleanup

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77000?usp=email )

Change subject: mb/intel/dcp847ske: Post-Haswell cleanup
......................................................................

mb/intel/dcp847ske: Post-Haswell cleanup

Now that Haswell-style mb_get_spd_map() is in place, remove
mainboard_get_spd() from "early southbridge" code where it never
should have belonged.

In mainboard_fill_pei_data(), fill only values that cannot be had
elsewhere, instead of redoing the entire structure.

Drop unused includes.

Change-Id: Idc545451dc4869db2861b57b5911446031b75f3e
Signed-off-by: Keith Hui 
---
M src/mainboard/intel/dcp847ske/early_southbridge.c
M src/mainboard/intel/dcp847ske/romstage.c
2 files changed, 8 insertions(+), 40 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/77000/1

diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index e2fd2aa..e0f27ba 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -2,7 +2,6 @@

#include <bootblock_common.h>
 #include <stdint.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>

#include "superio.h"
@@ -126,12 +125,6 @@
    hwm_init();
 }

-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x51, id_only);
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 #define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin }
 #include "usb.h"
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index 22af5ad..2a3ea94 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -1,46 +1,21 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-#include <arch/hpet.h>
-#include <stdint.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#if CONFIG(USE_NATIVE_RAMINIT)
-#include <northbridge/intel/sandybridge/raminit_native.h>
-#endif
+#include <string.h>
 #include <northbridge/intel/sandybridge/raminit.h>
-#include <southbridge/intel/bd82x6x/pch.h>

-#if !CONFIG(USE_NATIVE_RAMINIT)
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 0,
-		.gbe_enable = 1,
-		.max_ddr3_freq = 1333,
-		.usb_port_config = {
+	uint16_t usbcfg[16][3] = {
 #define USB_CONFIG(enabled, current, ocpin) { enabled, ocpin, 0x040 * current }
 #include "usb.h"
-		},
    };
-	*pei_data = pei_data_template;
+
+	memcpy(pei_data->usb_port_config, &usbcfg, sizeof(usbcfg));
+
+	pei_data->max_ddr3_freq = 1333;
+	pei_data->system_type = 0; // 0 Mobile, 1 Desktop/Server
+	pei_data->gbe_enable = 1;
 }
-#endif

void mb_get_spd_map(struct spd_info *spdi)
 {