Attention is currently required from: Reka Norman, Tim Wawrzynczak. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61141 )
Change subject: mb/google/nissa: Add devicetree ......................................................................
Patch Set 1:
(5 comments)
File src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/61141/comment/426824d8_1e4f5242 PS1, Line 4: register "pmc_gpe0_dw0" = "GPP_A" : register "pmc_gpe0_dw1" = "GPP_H" : register "pmc_gpe0_dw2" = "GPP_F"
Should these be sorted, or is it intentional to minimise the delta from brya?
These don't have to be sorted so bit of intention to minimize delta :)
https://review.coreboot.org/c/coreboot/+/61141/comment/a3bc15f2_7d8965bb PS1, Line 24: USB2_C1
Do we need to handle the fact that C1 and A1 may be used differently, or not at all, depending on th […]
We'll need to handle it once we have fw_config.
https://review.coreboot.org/c/coreboot/+/61141/comment/6b0f67b5_f271fe52 PS1, Line 58: register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" : register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
Where do these come from?
To be honest I couldn't find any information about this, thus copied from brya & adlrvp_n.
https://review.coreboot.org/c/coreboot/+/61141/comment/97654b03_4ff75d05 PS1, Line 72: Sub-board
Specifically it's used for the SAR sensor. Also, it looks like nivviks uses it for the MIPI WFC too.
Thanks for catching it, updated comments.
https://review.coreboot.org/c/coreboot/+/61141/comment/d3214b88_e4a91b7b PS1, Line 125: end : device
eMMC?
Done
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Kangheui Won (Code Review)