New patch to review for coreboot: 4c396e8 cpu/amd/model_10xxx: Determine single-link status of each CPU in _PSD generator

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10158

-gerrit

commit 4c396e878c006bd8cf19af95809c8a73b2cb3eb0
Author: Timothy Pearson 
Date:   Fri May 8 17:17:44 2015 -0500

cpu/amd/model_10xxx: Determine single-link status of each CPU in _PSD generator

The prior ACPI _PSD generator incorrectly assumed the active link count of each
    processor was identical.  Detect the link count on each node when generating the
    _PSD objects.

Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf9b
    Signed-off-by: Timothy Pearson 
---
 src/cpu/amd/model_10xxx/powernow_acpi.c | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c
index 6c8ed9d..1f05a4a 100644
--- a/src/cpu/amd/model_10xxx/powernow_acpi.c
+++ b/src/cpu/amd/model_10xxx/powernow_acpi.c
@@ -70,7 +70,7 @@ static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_p
    acpigen_write_PPC(pstate_num);

/* Write PSD indicating coordination type */
-	if ((single_link) && (mctGetLogicalCPUID(0) & AMD_DR_GT_Bx)) {
+	if ((single_link) && (mctGetLogicalCPUID(0) & (AMD_DR_GT_Bx | AMD_FAM15_ALL))) {
    	/* Revision C or greater single-link processor */
    	cpuid1 = cpuid(0x80000008);
    	acpigen_write_PSD_package(0, (cpuid1.ecx & 0xff) + 1, SW_ALL);
@@ -145,7 +145,10 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
    printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);

uint32_t dtemp;
+	uint8_t node_index;
    uint8_t node_count;
+	uint8_t cores_per_node;
+	uint8_t total_core_count;

/*
     * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
@@ -161,9 +164,9 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
    /* Get number of nodes */
    dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x60);
    node_count = ((dtemp & 0x70) >> 4) + 1;
+	cores_per_node = cmp_cap + 1;
    /* Compute total number of cores installed in system */
-	cmp_cap++;
-	cmp_cap *= node_count;
+	total_core_count = cores_per_node * node_count;

Pstate_num = 0;

@@ -191,10 +194,6 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
    uint32_t core_voltage;	/* multiplied by 10000 */
    uint8_t single_link;

-	/* Determine if this is a single-link system */
-	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x80);
-	single_link = !!(((dtemp & 0xff00) >> 8) == 0);
-
    /* Determine if this is a PVI or SVI system */
    dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);

@@ -297,9 +296,15 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
    char pscope[] = "\_PR";

acpigen_write_scope(pscope);
-	for (index = 0; index < cmp_cap; index++)
+	for (index = 0; index < total_core_count; index++) {
+		/* Determine if this is a single-link processor */
+		node_index = 0x18 + (index / cores_per_node);
+		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(node_index, 0)), 0x80);
+		single_link = !!(((dtemp & 0xff00) >> 8) == 0);
+
    	write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_power,
    			Pstate_latency, Pstate_control, Pstate_status,
    			index, pcontrol_blk, plen, onlyBSP, single_link);
+	}
    acpigen_pop_len();
 }