Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46845 )
Change subject: mb/google/jasperlake: Enable microcode update ......................................................................
mb/google/jasperlake: Enable microcode update
Adds flashmap descriptor with RW_UCODE_STAGED to enable microcode update with the top swap.
Change-Id: I4afcbc0bf5f9e703260192ef7e1c6575bb5633cf Signed-off-by: Sugnan Prabhu S sugnan.prabhu.s@intel.com --- M src/mainboard/intel/jasperlake_rvp/Kconfig A src/mainboard/intel/jasperlake_rvp/chromeos-ucode.fmd M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/bootblock/report_platform.c 4 files changed, 58 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46845/1
diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 1125a9b..bb31330 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -73,4 +73,12 @@ config TPM_TIS_ACPI_INTERRUPT int default 45 # GPE0_DW1_13 (GPP_H13) + +config FMDFILE + string "fmap description file with RW_UCODE_STAGED area in fmd format" + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-ucode.fmd" \ + if INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE + help + Top swap requires a fmap file with the RW_UCODE_STAGED area. + endif diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos-ucode.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos-ucode.fmd new file mode 100644 index 0000000..1cf3c72 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/chromeos-ucode.fmd @@ -0,0 +1,44 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x600000 { + SI_DESC@0x0 0x1000 + SI_EC@0x1000 0x80000 + SI_ME@0x81000 0x57F000 + } + SI_BIOS@0x600000 0xA00000 { + RW_SECTION_A@0x0 0x2cc000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x2bbfc0 + RW_FWID_A@0x2cbfc0 0x40 + } + RW_SECTION_B@0x2cc000 0x2cc000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x2bbfc0 + RW_FWID_B@0x2cbfc0 0x40 + } + RW_MISC@0x598000 0x38000 { + RW_UCODE_STAGED(PRESERVE)@0x0 0x8000 + UNIFIED_MRC_CACHE@0x8000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x28000 0x4000 + RW_SHARED@0x2c000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x30000 0x2000 + RW_NVRAM(PRESERVE)@0x32000 0x6000 + } + RW_LEGACY(CBFS)@0x5d0000 0x30000 + WP_RO@0x600000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 8efa361..0ff4734 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -23,6 +23,7 @@ select IDT_IN_EVERY_STAGE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE select IOAPIC select MRC_SETTINGS_PROTECT select PARALLEL_MP @@ -35,6 +36,7 @@ select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index beab782..c5e037f 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -8,6 +8,7 @@ #include <cpu/x86/name.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelbasecode/ucode_update.h> #include <intelblocks/mp_init.h> #include <soc/bootblock.h> #include <soc/pch.h> @@ -82,6 +83,9 @@ printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", cpu_id, cpu_type, get_current_microcode_rev());
+ if (CONFIG(INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE)) + check_ucode_and_update_top_swap(); + cpu_feature_flag = cpu_get_feature_flags_ecx(); aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
Hello build bot (Jenkins), Jamie Ryu, Rizwan Qureshi, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46845
to look at the new patch set (#2).
Change subject: mb/google/jasperlake: Enable microcode update ......................................................................
mb/google/jasperlake: Enable microcode update
Adds flashmap descriptor with RW_UCODE_STAGED to enable microcode update with the top swap.
Change-Id: I4afcbc0bf5f9e703260192ef7e1c6575bb5633cf Signed-off-by: Sugnan Prabhu S sugnan.prabhu.s@intel.com --- M src/mainboard/intel/jasperlake_rvp/Kconfig A src/mainboard/intel/jasperlake_rvp/chromeos-ucode.fmd M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/bootblock/report_platform.c 4 files changed, 55 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46845/2
Hello build bot (Jenkins), Jamie Ryu, Rizwan Qureshi, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46845
to look at the new patch set (#3).
Change subject: mb/google/jasperlake: Add check for microcode update ......................................................................
mb/google/jasperlake: Add check for microcode update
In case firmware interface table based firmware update feature is enabled, check that the microcode has been loaded via FIT, if not disable top-swap to allow RO microcode to be loaded on the next boot.
Change-Id: I4afcbc0bf5f9e703260192ef7e1c6575bb5633cf Signed-off-by: Sugnan Prabhu S sugnan.prabhu.s@intel.com --- M src/soc/intel/jasperlake/bootblock/report_platform.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46845/3
Hello build bot (Jenkins), Jamie Ryu, Rizwan Qureshi, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46845
to look at the new patch set (#4).
Change subject: mb/google/jasperlake: Add check for microcode update ......................................................................
mb/google/jasperlake: Add check for microcode update
In case firmware interface table based firmware update feature is enabled, check that the microcode has been loaded via FIT, if not disable top-swap to allow RO microcode to be loaded on the next boot.
Change-Id: I4afcbc0bf5f9e703260192ef7e1c6575bb5633cf Signed-off-by: Sugnan Prabhu S sugnan.prabhu.s@intel.com --- M src/soc/intel/jasperlake/bootblock/report_platform.c 1 file changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46845/4
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46845?usp=email )
Change subject: mb/google/jasperlake: Add check for microcode update ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Martin L Roth (Code Review) -
Sugnan Prabhu S (Code Review)