David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48976 )
Change subject: mb/google/volteer/var/voema: Update Aux settings for Port 0 ......................................................................
mb/google/volteer/var/voema: Update Aux settings for Port 0
On Voema port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping.
BUG=b:176462544 TEST=tested on voema
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f --- M src/mainboard/google/volteer/variants/voema/overridetree.cb 1 file changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/48976/1
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index f612beb..640f57d 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -5,6 +5,10 @@ # and controller 1 channel 0 and 1. register "CmdMirror" = "0x00000033"
+ register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + # Disable WLAN PCIE 7 register "PcieRpEnable[6]" = "0" register "PcieRpLtrEnable[6]" = "0" @@ -104,8 +108,6 @@ chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "5" register "usb3_port_number" = "1" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48976 )
Change subject: mb/google/volteer/var/voema: Update Aux settings for Port 0 ......................................................................
Patch Set 1: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48976 )
Change subject: mb/google/volteer/var/voema: Update Aux settings for Port 0 ......................................................................
Patch Set 1: Code-Review+2
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48976 )
Change subject: mb/google/volteer/var/voema: Update Aux settings for Port 0 ......................................................................
Patch Set 1: Code-Review+1
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48976 )
Change subject: mb/google/volteer/var/voema: Update Aux settings for Port 0 ......................................................................
Patch Set 1:
Could we merge this CL? Thanks.
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48976 )
Change subject: mb/google/volteer/var/voema: Update Aux settings for Port 0 ......................................................................
mb/google/volteer/var/voema: Update Aux settings for Port 0
On Voema port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping.
BUG=b:176462544 TEST=tested on voema
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48976 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Caveh Jalali caveh@chromium.org --- M src/mainboard/google/volteer/variants/voema/overridetree.cb 1 file changed, 4 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Paul Fagerburg: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index daea432..ff6b64b 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -5,6 +5,10 @@ # and controller 1 channel 0 and 1. register "CmdMirror" = "0x00000033"
+ register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + # Disable WLAN PCIE 7 register "PcieRpEnable[6]" = "0" register "PcieRpLtrEnable[6]" = "0" @@ -105,8 +109,6 @@ chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "5" register "usb3_port_number" = "1" - # SBU is fixed, HSL follows CC - register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn