Change in coreboot[master]: soc/amd/cezanne: Add GRXS and GTXS method

[Ivy Jian (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held.
Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52184 )

Change subject: soc/amd/cezanne: Add GRXS and GTXS method
......................................................................

soc/amd/cezanne: Add GRXS and GTXS method

Add GRXS and GTXS support.

BUG=none
BRANCH=none
TEST=Confirm that CTXS and STXS is functional in SSDT.dsl

Signed-off-by: Ivy Jian 
Change-Id: I2e3512562f92de230cf2e6967ec90527fb3d62ee
---
M src/soc/amd/cezanne/acpi.c
1 file changed, 48 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/52184/1

diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c
index 45cf1bc..bd3daf9 100644
--- a/src/soc/amd/cezanne/acpi.c
+++ b/src/soc/amd/cezanne/acpi.c
@@ -4,6 +4,7 @@

#include <acpi/acpi.h>
 #include <amdblocks/acpi.h>
+#include <acpi/acpigen.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/ioapic.h>
 #include <arch/ioapic.h>
@@ -121,3 +122,50 @@
    fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
    fadt->x_gpe0_blk.addrh = 0x0;
 }
+
+static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
+{
+	if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
+		printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
+					" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
+		return -1;
+	}
+	/* op (gpio_num) */
+	acpigen_emit_namestring(op);
+	acpigen_write_integer(gpio_num);
+	return 0;
+}
+
+static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
+{
+	if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
+		printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
+					" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
+		return -1;
+	}
+	/* Store (op (gpio_num), Local0) */
+	acpigen_write_store();
+	acpigen_soc_gpio_op(op, gpio_num);
+	acpigen_emit_byte(LOCAL0_OP);
+	return 0;
+}
+
+int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_get_gpio_state("\_SB.GRXS", gpio_num);
+}
+
+int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_get_gpio_state("\_SB.GTXS", gpio_num);
+}
+
+int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_gpio_op("\_SB.STXS", gpio_num);
+}
+
+int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_gpio_op("\_SB.CTXS", gpio_num);
+}