Change in coreboot[master]: soc/intel/tigerlake: Enable SATA

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Wonkyu Kim (Code Review)

22 Jan 2020 22 Jan '20

5:55 a.m.

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38504 )

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

soc/intel/tigerlake: Enable SATA

BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory

Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38504/1

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index fe59ac1..2fb9318 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -121,6 +121,20 @@ /* PCH UART selection for FSP Debug */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;

+ /* SATA */ + dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); + if (!dev) + params->SataEnable = 0; + else { + params->SataEnable = dev->enabled; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + } + mainboard_silicon_init_params(params); }

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build bot (Jenkins) (Code Review)

22 Jan 22 Jan

5:55 a.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38504 )

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

Patch Set 1:

(25 comments)

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 124: /* SATA */ code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 125: dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 125: dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 126: if (!dev) code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 126: if (!dev) please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 127: params->SataEnable = 0; code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 127: params->SataEnable = 0; please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 128: else { code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 128: else { please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 129: params->SataEnable = dev->enabled; code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 129: params->SataEnable = dev->enabled; please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 130: params->SataMode = config->SataMode; code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 130: params->SataMode = config->SataMode; please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 131: params->SataSalpSupport = config->SataSalpSupport; code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 131: params->SataSalpSupport = config->SataSalpSupport; please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 132: memcpy(params->SataPortsEnable, config->SataPortsEnable, code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 132: memcpy(params->SataPortsEnable, config->SataPortsEnable, please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 133: sizeof(params->SataPortsEnable)); code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 133: sizeof(params->SataPortsEnable)); please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 134: memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 134: memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 135: sizeof(params->SataPortsDevSlp)); code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 135: sizeof(params->SataPortsDevSlp)); please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 136: } code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 136: } please, no spaces at the start of a line

Wonkyu Kim (Code Review)

6:01 a.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38504 )

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

Patch Set 1:

(25 comments)

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 124: /* SATA */

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 125: dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 125: dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 126: if (!dev)

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 126: if (!dev)

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 127: params->SataEnable = 0;

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 127: params->SataEnable = 0;

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 128: else {

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 128: else {

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 129: params->SataEnable = dev->enabled;

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 129: params->SataEnable = dev->enabled;

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 130: params->SataMode = config->SataMode;

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 130: params->SataMode = config->SataMode;

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 131: params->SataSalpSupport = config->SataSalpSupport;

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 131: params->SataSalpSupport = config->SataSalpSupport;

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 132: memcpy(params->SataPortsEnable, config->SataPortsEnable,

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 132: memcpy(params->SataPortsEnable, config->SataPortsEnable,

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 133: sizeof(params->SataPortsEnable));

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 133: sizeof(params->SataPortsEnable));

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 134: memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 134: memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 135: sizeof(params->SataPortsDevSlp));

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 135: sizeof(params->SataPortsDevSlp));

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 136: }

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/1/src/soc/intel/tigerlake/fsp... PS1, Line 136: }

...

code indent should use tabs where possible

Ack

Wonkyu Kim (Code Review)

6:01 a.m.

Hello Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38504

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

soc/intel/tigerlake: Enable SATA

BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory

Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38504/2

build bot (Jenkins) (Code Review)

6:01 a.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38504 )

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38504/2/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38504/2/src/soc/intel/tigerlake/fsp... PS2, Line 134: memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38504/2/src/soc/intel/tigerlake/fsp... PS2, Line 134: memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, please, no spaces at the start of a line

Wonkyu Kim (Code Review)

6:20 a.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38504

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

soc/intel/tigerlake: Enable SATA

BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory

Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38504/3

Wonkyu Kim (Code Review)

6:20 a.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38504 )

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

Patch Set 3: Code-Review+1

(2 comments)

https://review.coreboot.org/c/coreboot/+/38504/2/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38504/2/src/soc/intel/tigerlake/fsp... PS2, Line 134: memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38504/2/src/soc/intel/tigerlake/fsp... PS2, Line 134: memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,

...

code indent should use tabs where possible

Ack

Subrata Banik (Code Review)

7:32 a.m.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38504 )

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

Patch Set 3: Code-Review+2

Pratikkumar V Prajapati (Code Review)

23 Jan 23 Jan

12:16 a.m.

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38504 )

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38504/3//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38504/3//COMMIT_MSG@8 PS3, Line 8: : BUG=none : BRANCH=none : TEST=Build and boot tigerlake rvp board with SATA memory please add some lines about what changes are made in code.

Wonkyu Kim (Code Review)

5:27 p.m.

Hello Srinidhi N Kaushik, Raj Astekar, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Shaunak Saha, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38504

to look at the new patch set (#4).

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

soc/intel/tigerlake: Enable SATA

Configure SATA FSP UPD according to mainboard design.

BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory

Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38504/4

-- To view, visit https://review.coreboot.org/c/coreboot/+/38504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e Gerrit-Change-Number: 38504 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Raj Astekar raj.astekar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-CC: caveh jalali caveh@chromium.org Gerrit-MessageType: newpatchset

Wonkyu Kim (Code Review)

5:27 p.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38504 )

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38504/3//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38504/3//COMMIT_MSG@8 PS3, Line 8: : BUG=none : BRANCH=none : TEST=Build and boot tigerlake rvp board with SATA memory

...

please add some lines about what changes are made in code.

Ack

Nick Vaccaro (Code Review)

24 Jan 24 Jan

8:13 a.m.

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38504 )

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

Patch Set 4: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/38504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e Gerrit-Change-Number: 38504 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Raj Astekar raj.astekar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-CC: caveh jalali caveh@chromium.org Gerrit-Comment-Date: Fri, 24 Jan 2020 08:13:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Subrata Banik (Code Review)

9:52 a.m.

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38504 )

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

soc/intel/tigerlake: Enable SATA

Configure SATA FSP UPD according to mainboard design.

BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board with SATA memory

Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38504 Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Subrata Banik subrata.banik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/fsp_params_tgl.c 1 file changed, 14 insertions(+), 0 deletions(-)

Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Nick Vaccaro: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index fe59ac1..305748e 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -121,6 +121,20 @@ /* PCH UART selection for FSP Debug */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;

-- To view, visit https://review.coreboot.org/c/coreboot/+/38504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e Gerrit-Change-Number: 38504 Gerrit-PatchSet: 5 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Raj Astekar raj.astekar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-CC: caveh jalali caveh@chromium.org Gerrit-MessageType: merged

9elements QA (Code Review)

10:25 a.m.

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38504 )

Change subject: soc/intel/tigerlake: Enable SATA ......................................................................

Patch Set 5:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/236 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/235 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/234

Please note: This test is under development and might not be accurate at all!

-- To view, visit https://review.coreboot.org/c/coreboot/+/38504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e Gerrit-Change-Number: 38504 Gerrit-PatchSet: 5 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Raj Astekar raj.astekar@intel.com Gerrit-Reviewer: Shaunak Saha shaunak.saha@intel.com Gerrit-Reviewer: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: 9elements QA hardwaretestrobot@gmail.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-CC: caveh jalali caveh@chromium.org Gerrit-Comment-Date: Fri, 24 Jan 2020 10:25:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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9elements QA (Code Review)
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