New patch to review for coreboot: 4449761 src: Remove 'CONFIG_CHROMEOS' guard around header inclusion
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6256
-gerrit
commit 44497617f9d4733a0c84b858e697e91819fa4395 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Fri Jul 11 05:49:52 2014 +1000
src: Remove 'CONFIG_CHROMEOS' guard around header inclusion
No need to guard the pre-processor with the pre-processor.
Change-Id: I3eab8b55dc104927a0c6bbe6e09ff9083bccf8d2 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/arch/x86/boot/smbios.c | 3 +-- src/cpu/intel/haswell/romstage.c | 4 ---- src/lib/bootmode.c | 2 -- src/lib/coreboot_table.c | 2 -- src/northbridge/intel/haswell/mrccache.c | 2 -- src/northbridge/intel/sandybridge/mrccache.c | 2 -- src/soc/intel/baytrail/mrc_cache.c | 2 -- src/soc/intel/baytrail/romstage/romstage.c | 2 -- src/southbridge/intel/bd82x6x/me.c | 2 -- src/southbridge/intel/fsp_bd82x6x/me.c | 2 -- src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 2 -- src/southbridge/intel/ibexpeak/me.c | 2 -- src/southbridge/intel/lynxpoint/me_9.x.c | 2 -- 13 files changed, 1 insertion(+), 28 deletions(-)
diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index ce47a8b..c8ca11c 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -30,9 +30,8 @@ #include <cbfs_core.h> #include <arch/byteorder.h> #include <elog.h> -#if CONFIG_CHROMEOS + #include <vendorcode/google/chromeos/gnvs.h> -#endif
static u8 smbios_checksum(u8 *p, u32 length) { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9e27668..541b903 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -36,12 +36,8 @@ #include <ramstage_cache.h> #include <romstage_handoff.h> #include <reset.h> -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> -#endif -#if CONFIG_EC_GOOGLE_CHROMEEC #include <ec/google/chromeec/ec.h> -#endif #include "haswell.h" #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 9818490..3d4d871 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -19,9 +19,7 @@
#include <rules.h> #include <bootmode.h> -#if CONFIG_CHROMEOS || CONFIG_VBOOT_VERIFY_FIRMWARE #include <vendorcode/google/chromeos/chromeos.h> -#endif
#if CONFIG_BOOTMODE_STRAPS int developer_mode_enabled(void) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 1e1ad82..0745f4d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -31,13 +31,11 @@ #include <cbfs.h> #include <cbmem.h> #include <bootmem.h> -#if CONFIG_CHROMEOS #if CONFIG_GENERATE_ACPI_TABLES #include <arch/acpi.h> #endif #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> -#endif #if CONFIG_ARCH_X86 #include <cpu/x86/mtrr.h> #endif diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index a921e04..3374b98 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -29,9 +29,7 @@ #include "haswell.h" #include <spi-generic.h> #include <spi_flash.h> -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/fmap.h> -#endif
/* convert a pointer to flash area into the offset inside the flash */ static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..7951aa9 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -29,9 +29,7 @@ #include "sandybridge.h" #include <spi-generic.h> #include <spi_flash.h> -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/fmap.h> -#endif
/* convert a pointer to flash area into the offset inside the flash */ static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { diff --git a/src/soc/intel/baytrail/mrc_cache.c b/src/soc/intel/baytrail/mrc_cache.c index ae0afe7..28a8955 100644 --- a/src/soc/intel/baytrail/mrc_cache.c +++ b/src/soc/intel/baytrail/mrc_cache.c @@ -21,9 +21,7 @@ #include <console/console.h> #include <cbmem.h> #include <ip_checksum.h> -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/fmap.h> -#endif #include <baytrail/mrc_cache.h>
#define MRC_DATA_ALIGN 0x1000 diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 3a1d65d..d9f29b1 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -26,9 +26,7 @@ #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> -#if CONFIG_EC_GOOGLE_CHROMEEC #include <ec/google/chromeec/ec.h> -#endif #include <elog.h> #include <ramstage_cache.h> #include <romstage_handoff.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 44c7273..f38063b 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -47,9 +47,7 @@ #include "me.h" #include "pch.h"
-#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/gnvs.h> -#endif
#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index 2282378..deafbc2 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -46,9 +46,7 @@ #include "me.h" #include "pch.h"
-#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/gnvs.h> -#endif
#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index 1c2ab34..65b9f6d 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -45,10 +45,8 @@ #include "me.h" #include "pch.h"
-#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> -#endif
#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 99920f5..6b8da5b 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -47,9 +47,7 @@ #include "me.h" #include "pch.h"
-#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/gnvs.h> -#endif
#ifndef __SMM__ /* Path that the BIOS should take based on ME state */ diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index c8ff913..ed39636 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -42,10 +42,8 @@ #include "me.h" #include "pch.h"
-#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> -#endif
#ifndef __SMM__ /* Path that the BIOS should take based on ME state */
-
Edward O'Callaghan