Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82092?usp=email )
Change subject: soc/intel/xeon_sp: Add get_cxl_mode ......................................................................
soc/intel/xeon_sp: Add get_cxl_mode
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes.
Add get_cxl_mode so that SoC codes do not need to get this configuration from VPD any more.
Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0 Signed-off-by: Shuo Liu shuo.liu@intel.com --- M src/mainboard/intel/archercity_crb/Makefile.mk A src/mainboard/intel/archercity_crb/util.c M src/mainboard/inventec/transformers/Makefile.mk A src/mainboard/inventec/transformers/util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/util.c 8 files changed, 71 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/82092/1
diff --git a/src/mainboard/intel/archercity_crb/Makefile.mk b/src/mainboard/intel/archercity_crb/Makefile.mk index 4c7a7be..b28d73c 100644 --- a/src/mainboard/intel/archercity_crb/Makefile.mk +++ b/src/mainboard/intel/archercity_crb/Makefile.mk @@ -2,5 +2,7 @@
bootblock-y += bootblock.c romstage-y += romstage.c +romstage-y += util.c ramstage-y += ramstage.c +ramstage-y += util.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/intel/archercity_crb/util.c b/src/mainboard/intel/archercity_crb/util.c new file mode 100644 index 0000000..5197b23 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/util.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/ocp/include/vpd.h> +#include <soc/chip_common.h> +#include <soc/util.h> + +#if CONFIG(SOC_INTEL_HAS_CXL) +enum xeonsp_cxl_mode get_cxl_mode(void) +{ + int ocp_cxl_mode = get_cxl_mode_from_vpd(); + switch (ocp_cxl_mode) { + case CXL_SYSTEM_MEMORY: + return XEONSP_CXL_SYS_MEM; + case CXL_SPM: + return XEONSP_CXL_SP_MEM; + default: + return XEONSP_CXL_DISABLED; + } +} +#endif diff --git a/src/mainboard/inventec/transformers/Makefile.mk b/src/mainboard/inventec/transformers/Makefile.mk index ecb6ef2..eb859d3 100644 --- a/src/mainboard/inventec/transformers/Makefile.mk +++ b/src/mainboard/inventec/transformers/Makefile.mk @@ -2,5 +2,7 @@
bootblock-y += bootblock.c romstage-y += romstage.c +romstage-y += util.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi.c +ramstage-y += util.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/inventec/transformers/util.c b/src/mainboard/inventec/transformers/util.c new file mode 100644 index 0000000..5197b23 --- /dev/null +++ b/src/mainboard/inventec/transformers/util.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/ocp/include/vpd.h> +#include <soc/chip_common.h> +#include <soc/util.h> + +#if CONFIG(SOC_INTEL_HAS_CXL) +enum xeonsp_cxl_mode get_cxl_mode(void) +{ + int ocp_cxl_mode = get_cxl_mode_from_vpd(); + switch (ocp_cxl_mode) { + case CXL_SYSTEM_MEMORY: + return XEONSP_CXL_SYS_MEM; + case CXL_SPM: + return XEONSP_CXL_SP_MEM; + default: + return XEONSP_CXL_DISABLED; + } +} +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 5fd5dc6..5bdc87f 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -33,6 +33,12 @@ path->domain.domain = dp.domain_path; };
+enum xeonsp_cxl_mode { + XEONSP_CXL_DISABLED = 0, + XEONSP_CXL_SYS_MEM, + XEONSP_CXL_SP_MEM, +}; + /* * Every STACK can have multiple PCI domains with an unique domain type. * This is only of cosmetic nature and generates more readable ACPI code, diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 177d6d5..734455a 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -28,4 +28,6 @@ bool is_iio_cxl_stack_res(const xSTACK_RES *res); void bios_done_msr(void *unused);
+enum xeonsp_cxl_mode get_cxl_mode(void); + #endif diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index a177a89..c5d1d78 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -6,8 +6,8 @@ #include <cpu/x86/lapic_def.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <drivers/ocp/include/vpd.h> #include <soc/acpi.h> +#include <soc/chip_common.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -286,22 +286,20 @@ if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) continue;
- if (CONFIG(OCP_VPD)) { - unsigned long flags = IORESOURCE_CACHEABLE; - int cxl_mode = get_cxl_mode_from_vpd(); - if (cxl_mode == CXL_SPM) - flags |= IORESOURCE_SOFT_RESERVE; - else - flags |= IORESOURCE_STORED; + unsigned long flags = IORESOURCE_CACHEABLE; + int cxl_mode = get_cxl_mode(); + if (cxl_mode == XEONSP_CXL_SP_MEM) + flags |= IORESOURCE_SOFT_RESERVE; + else + flags |= IORESOURCE_STORED;
- res = fixed_mem_range_flags(dev, index++, - (uint64_t)pds.pds[i].base << 26, - (uint64_t)pds.pds[i].size << 26, flags); - if (cxl_mode == CXL_SPM) - LOG_RESOURCE("specific_purpose_memory", dev, res); - else - LOG_RESOURCE("CXL_memory", dev, res); - } + res = fixed_mem_range_flags(dev, index++, + (uint64_t)pds.pds[i].base << 26, + (uint64_t)pds.pds[i].size << 26, flags); + if (cxl_mode == XEONSP_CXL_SP_MEM) + LOG_RESOURCE("specific_purpose_memory", dev, res); + else + LOG_RESOURCE("CXL_memory", dev, res); } } else { /* 4GiB -> TOHM */ diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 81dc77d..5c63f18 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -237,3 +237,8 @@ set_bios_init_completion_for_package(sbsp_socket_id); } #endif + +__weak enum xeonsp_cxl_mode get_cxl_mode(void) +{ + return XEONSP_CXL_DISABLED; +}