Change in coreboot[master]: sb/intel/bd82x6x: Relocate `intel_me_finalize_smm` function

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45260 )

Change subject: sb/intel/bd82x6x: Relocate `intel_me_finalize_smm` function
......................................................................

sb/intel/bd82x6x: Relocate `intel_me_finalize_smm` function

This allows us to hide two small functions, which have been inlined.

Change-Id: Ifc787c903380f748812f1ae5bf627613fb5c3987
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me.h
M src/southbridge/intel/bd82x6x/me_common.c
3 files changed, 46 insertions(+), 47 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/45260/1

diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 854698b..af411cc 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -111,7 +111,7 @@
 #ifdef __SIMPLE_DEVICE__

/* Send END OF POST message to the ME */
-static int intel_me7_send_eop(void)
+int intel_me7_send_eop(void)
 {
    struct mkhi_header mkhi = {
    	.group_id	= MKHI_GROUP_ID_GEN,
@@ -134,48 +134,6 @@
    return 0;
 }

-void intel_me_finalize_smm(void)
-{
-	struct me_hfs hfs;
-	u32 reg32;
-
-	update_mei_base_address();
-
-	/* S3 path will have hidden this device already */
-	if (!is_mei_base_address_valid())
-		return;
-
-	/* Make sure ME is in a mode that expects EOP */
-	reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
-	memcpy(&hfs, &reg32, sizeof(u32));
-
-	/* Abort and leave device alone if not normal mode */
-	if (hfs.fpt_bad ||
-	    hfs.working_state != ME_HFS_CWS_NORMAL ||
-	    hfs.operation_mode != ME_HFS_MODE_NORMAL)
-		return;
-
-	/* Try to send EOP command so ME stops accepting other commands */
-	const u16 did = pci_read_config16(PCH_ME_DEV, PCI_DEVICE_ID);
-	switch (did) {
-	case 0x1c3a:
-		intel_me7_send_eop();
-		break;
-	case 0x1e3a:
-		intel_me8_send_eop();
-		break;
-	default:
-		printk(BIOS_ERR, "No EOP handler for ME %04x.\n", did);
-	}
-
-	/* Make sure IO is disabled */
-	pci_and_config16(PCH_ME_DEV, PCI_COMMAND,
-			 ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
-
-	/* Hide the PCI device */
-	RCBA32_OR(FD2, PCH_DISABLE_MEI1);
-}
-
 #else

/* Determine the path that we should take based on ME status */
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index 8dd34bc..dca1d3e 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -242,8 +242,6 @@
 int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
    	 void *req_data, void *rsp_data, int rsp_bytes);

-void update_mei_base_address(void);
-bool is_mei_base_address_valid(void);
 int intel_mei_setup(struct device *dev);
 int intel_me_extend_valid(struct device *dev);
 void intel_me_hide(struct device *dev);
@@ -258,6 +256,7 @@

void intel_me_finalize_smm(void);

+int intel_me7_send_eop(void);
 int intel_me8_send_eop(void);

typedef struct {
diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c
index 1ce61a1..94e5c9a 100644
--- a/src/southbridge/intel/bd82x6x/me_common.c
+++ b/src/southbridge/intel/bd82x6x/me_common.c
@@ -322,16 +322,58 @@

#ifdef __SIMPLE_DEVICE__

-void update_mei_base_address(void)
+static inline void update_mei_base_address(void)
 {
    mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
 }

-bool is_mei_base_address_valid(void)
+static inline bool is_mei_base_address_valid(void)
 {
    return mei_base_address && mei_base_address != (u32 *)0xfffffff0;
 }

+void intel_me_finalize_smm(void)
+{
+	struct me_hfs hfs;
+	u32 reg32;
+
+	update_mei_base_address();
+
+	/* S3 path will have hidden this device already */
+	if (!is_mei_base_address_valid())
+		return;
+
+	/* Make sure ME is in a mode that expects EOP */
+	reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+	memcpy(&hfs, &reg32, sizeof(u32));
+
+	/* Abort and leave device alone if not normal mode */
+	if (hfs.fpt_bad ||
+	    hfs.working_state != ME_HFS_CWS_NORMAL ||
+	    hfs.operation_mode != ME_HFS_MODE_NORMAL)
+		return;
+
+	/* Try to send EOP command so ME stops accepting other commands */
+	const u16 did = pci_read_config16(PCH_ME_DEV, PCI_DEVICE_ID);
+	switch (did) {
+	case 0x1c3a:
+		intel_me7_send_eop();
+		break;
+	case 0x1e3a:
+		intel_me8_send_eop();
+		break;
+	default:
+		printk(BIOS_ERR, "No EOP handler for ME %04x.\n", did);
+	}
+
+	/* Make sure IO is disabled */
+	pci_and_config16(PCH_ME_DEV, PCI_COMMAND,
+			 ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
+
+	/* Hide the PCI device */
+	RCBA32_OR(FD2, PCH_DISABLE_MEI1);
+}
+
 #else

/* Prepare ME for MEI messages */

[Angel Pons (Code Review)]

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45260 )

Change subject: sb/intel/bd82x6x: Relocate `intel_me_finalize_smm` function
......................................................................

Abandoned

Rotten