Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27042
Change subject: sb/intel/common/rcba_pirq.c: Use common RCBA acces MACROs ......................................................................
sb/intel/common/rcba_pirq.c: Use common RCBA acces MACROs
Change-Id: I2fe8d8388cb96e42af4f9be251a41cceeb2e4710 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/common/rcba_pirq.h 2 files changed, 1 insertion(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/27042/1
diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 7f97971..366fe08 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rcba_pirq.h> +#include <southbridge/intel/common/rcba.h>
#define MAX_SLOT 31 #define MIN_SLOT 19 diff --git a/src/southbridge/intel/common/rcba_pirq.h b/src/southbridge/intel/common/rcba_pirq.h index cf76fb3..e5ac409 100644 --- a/src/southbridge/intel/common/rcba_pirq.h +++ b/src/southbridge/intel/common/rcba_pirq.h @@ -37,8 +37,4 @@ #define D20IR 0x3160 /* 16bit */ #define D19IR 0x3168 /* 16bit */
-#define DEFAULT_RCBA 0xfed1c000 - -#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x)))) - #endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */