[M] Change in coreboot[main]: mb/google/brya: Remove baseboard-specific FMD names

[Dinesh Gehlot (Code Review)]

Attention is currently required from: Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik.

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81676?usp=email )

Change subject: mb/google/brya: Remove baseboard-specific FMD names
......................................................................

mb/google/brya: Remove baseboard-specific FMD names

This patch renames the 16MB FMD file to remove the baseboard-specific
name 'Nissa'. This allows other supported baseboards to utilize the
16MB SPI flash. Additionally, this patch removes the Nissa-specific
32MB FMD file, as the Nissa board only uses a 16MB SPI flash. Other
Brya boards are using the existing generic 32MB chromeos.fmd file.

TEST=Build and boot Nivviks.

Change-Id: I9151a4bcbe9cc084cc19b1a3e91c0321fe4dcc37
Signed-off-by: Dinesh Gehlot 
---
M src/mainboard/google/brya/Kconfig
R src/mainboard/google/brya/chromeos-16MiB-debugfsp.fmd
R src/mainboard/google/brya/chromeos-16MiB.fmd
D src/mainboard/google/brya/chromeos-nissa-32MiB.fmd
4 files changed, 2 insertions(+), 54 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/81676/1

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 732a9ea..c890dfe 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -636,9 +636,8 @@

config FMDFILE
    default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if CHROMEOS && BOARD_GOOGLE_BRASK
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-16MiB-debugfsp.fmd" if CHROMEOS && BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384 && BUILDING_WITH_DEBUG_FSP
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-16MiB.fmd" if CHROMEOS && BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-32MiB.fmd" if CHROMEOS && BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_32768
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB-debugfsp.fmd" if CHROMEOS && BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384 && BUILDING_WITH_DEBUG_FSP
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if CHROMEOS && BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384
    default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS

config TPM_TIS_ACPI_INTERRUPT
diff --git a/src/mainboard/google/brya/chromeos-nissa-16MiB-debugfsp.fmd b/src/mainboard/google/brya/chromeos-16MiB-debugfsp.fmd
similarity index 100%
rename from src/mainboard/google/brya/chromeos-nissa-16MiB-debugfsp.fmd
rename to src/mainboard/google/brya/chromeos-16MiB-debugfsp.fmd
diff --git a/src/mainboard/google/brya/chromeos-nissa-16MiB.fmd b/src/mainboard/google/brya/chromeos-16MiB.fmd
similarity index 100%
rename from src/mainboard/google/brya/chromeos-nissa-16MiB.fmd
rename to src/mainboard/google/brya/chromeos-16MiB.fmd
diff --git a/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd b/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd
deleted file mode 100644
index 00e7997..0000000
--- a/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd
+++ /dev/null
@@ -1,51 +0,0 @@
-FLASH 32M {
-	SI_ALL 3712K {
-		SI_DESC 4K
-		SI_ME
-	}
-	SI_BIOS 29056K {
-		RW_SECTION_A 4376K {
-			VBLOCK_A 8K
-			FW_MAIN_A(CBFS)
-			RW_FWID_A 64
-		}
-		RW_LEGACY(CBFS) 1M
-		RW_MISC 152K {
-			UNIFIED_MRC_CACHE(PRESERVE) 128K {
-				RECOVERY_MRC_CACHE 64K
-				RW_MRC_CACHE 64K
-			}
-			RW_ELOG(PRESERVE) 4K
-			RW_SHARED 4K {
-				SHARED_DATA 4K
-			}
-			RW_VPD(PRESERVE) 8K
-			RW_NVRAM(PRESERVE) 8K
-		}
-		# RW UNUSED Region 1.
-		RW_UNUSED_1 7120K
-		# This section starts at the 16M boundary in SPI flash.
-		# ADL does not support a region crossing this boundary,
-		# because the SPI flash is memory-mapped into two non-
-		# contiguous windows.
-		RW_SECTION_B 4376K {
-			VBLOCK_B 8K
-			FW_MAIN_B(CBFS)
-			RW_FWID_B 64
-		}
-		# RW UNUSED Region 2.
-		RW_UNUSED_2 7912K
-		# Make WP_RO region align with SPI vendor
-		# memory protected range specification.
-		WP_RO 4M {
-			RO_VPD(PRESERVE) 16K
-			RO_GSCVD 8K
-			RO_SECTION {
-				FMAP 2K
-				RO_FRID 64
-				GBB@4K 12K
-				COREBOOT(CBFS)
-			}
-		}
-	}
-}