Change in coreboot[master]: sb/amd/cimx/sb800: add C bootblock southbridge initialization
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37329 )
Change subject: sb/amd/cimx/sb800: add C bootblock southbridge initialization ......................................................................
sb/amd/cimx/sb800: add C bootblock southbridge initialization
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ie81198f5034a84d319ee7143aa032433f82be254 --- M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c 2 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/37329/1
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 418110b..ccb3a2a 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -16,6 +16,10 @@
# SB800 Platform Files
+ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +endif + romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c smbus_spd.c diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 28b37c3..110b7e10 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -114,3 +114,13 @@ enable_spi_fast_mode(); enable_clocks(); } + +#if !CONFIG(ROMCC_BOOTBLOCK) +#include <bootblock_common.h> +#include <arch/io.h> + +void bootblock_soc_early_init(void) +{ + bootblock_southbridge_init(); +} +#endif
Kyösti Mälkki has uploaded a new patch set (#2) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/37329 )
Change subject: sb/amd/cimx/sb800: add C bootblock southbridge initialization ......................................................................
sb/amd/cimx/sb800: add C bootblock southbridge initialization
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ie81198f5034a84d319ee7143aa032433f82be254 --- M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c 2 files changed, 23 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/37329/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37329 )
Change subject: sb/amd/cimx/sb800: add C bootblock southbridge initialization ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37329/2/src/southbridge/amd/cimx/sb... File src/southbridge/amd/cimx/sb800/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37329/2/src/southbridge/amd/cimx/sb... PS2, Line 129: bootblock_southbridge_init(); We need to check what sb_poweron_init() does and if it is required in bootblock already.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37329 )
Change subject: sb/amd/cimx/sb800: add C bootblock southbridge initialization ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37329/2/src/southbridge/amd/cimx/sb... File src/southbridge/amd/cimx/sb800/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37329/2/src/southbridge/amd/cimx/sb... PS2, Line 129: bootblock_southbridge_init();
We need to check what sb_poweron_init() does and if it is required in bootblock already.
It does lots of things: PMIOA programming, ALINK configuration, SPI fast speed configuration, legacy_free option handling for LPC decoding, some PCI devices configuration (SATA, LPC, P2P).
Maybe not necessarily in bootblock, but most likely before AGESA.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37329 )
Change subject: sb/amd/cimx/sb800: add C bootblock southbridge initialization ......................................................................
Patch Set 5: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37329 )
Change subject: sb/amd/cimx/sb800: add C bootblock southbridge initialization ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37329/2/src/southbridge/amd/cimx/sb... File src/southbridge/amd/cimx/sb800/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37329/2/src/southbridge/amd/cimx/sb... PS2, Line 129: bootblock_southbridge_init();
It does lots of things: PMIOA programming, ALINK configuration, SPI fast speed configuration, legacy […]
Ok. Sounds like serial port behind LPC would not require the call to be made.
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37329 )
Change subject: sb/amd/cimx/sb800: add C bootblock southbridge initialization ......................................................................
sb/amd/cimx/sb800: add C bootblock southbridge initialization
TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ie81198f5034a84d319ee7143aa032433f82be254 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37329 Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/amd/cimx/sb800/Makefile.inc M src/southbridge/amd/cimx/sb800/bootblock.c 2 files changed, 23 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 418110b..ccb3a2a 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -16,6 +16,10 @@
# SB800 Platform Files
+ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +endif + romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c smbus_spd.c diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 28b37c3..b4f03da 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -79,18 +79,21 @@ pci_io_write_config32(dev, 0xa0, save); }
-static void enable_clocks(void) +static void enable_acpimmio_decode_pm24(void) { u8 reg8; - u32 reg32; - volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40);
- // Program AcpiMmioEn to enable MMIO access to MiscCntrl register outb(0x24, 0xCD6); reg8 = inb(0xCD7); reg8 |= 1; reg8 &= ~(1 << 1); outb(reg8, 0xCD7); +} + +static void enable_clocks(void) +{ + u32 reg32; + volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40);
// Program SB800 MiscClkCntrl register to configure clock output on the // 14M_25M_48M_OSC ball usually used for the Super-I/O. @@ -112,5 +115,17 @@ enable_rom(); enable_prefetch(); enable_spi_fast_mode(); + + // Program AcpiMmioEn to enable MMIO access to MiscCntrl register + enable_acpimmio_decode_pm24(); enable_clocks(); } + +#if !CONFIG(ROMCC_BOOTBLOCK) +#include <bootblock_common.h> + +void bootblock_soc_early_init(void) +{ + bootblock_southbridge_init(); +} +#endif
-
Kyösti Mälkki (Code Review) -
Michał Żygowski (Code Review)