New patch to review for coreboot: b868e6e [NOTFORMERGE] gizmosphere/gizmo/mptable.c: Program PIC mode correctly

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5695

-gerrit

commit b868e6e363e771f3ec631b82f81e2ead85691be2
Author: Paul Menzel 
Date:   Thu May 8 08:46:16 2014 +0200

[NOTFORMERGE] gizmosphere/gizmo/mptable.c: Program PIC mode correctly

Ported Scott’s first patch for ASRock E350M1 to Gizmo.

Needs testing and setup should be moved to southbridge code so all boards profit.

Change-Id: Id4cf3f84744e844f869a7898b62f36f5e4c6d90a
    Signed-off-by: Paul Menzel 
---
 src/mainboard/gizmosphere/gizmo/mptable.c | 37 +++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c
index cc9e627..f6f37e4 100755
--- a/src/mainboard/gizmosphere/gizmo/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo/mptable.c
@@ -34,6 +34,7 @@ extern u32 apicid_sb800;
 extern u32 bus_type[256];
 extern u32 sbdn_sb800;

+/* SB800 interrupt routing register values: APIC mode */
 u8 intr_data[] = {
    [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,	/* INTA# - INTH# */
    [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,	/* Misc-nil,0,1,2, INT from Serial irq */
@@ -49,6 +50,17 @@ u8 intr_data[] = {
    0x10, 0x11, 0x12, 0x13
 };

+/* SB800 interrupt routing register values: PIC mode */
+u8 intr_data_pic[] = {
+	0x0B, 0x0A, 0x0B, 0x0A, 0x1F, 0x1F, 0x1F, 0x1F,	// 0x00
+	0x00, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,	// 0x08
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,	// 0x10
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,	// 0x18
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,	// 0x20
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,	// 0x28
+	0x0B, 0x0A, 0x0B, 0x0A, 0x1F, 0x1F, 0x1F, 0x1F	// 0x30
+};
+
 static void *smp_write_config_table(void *v)
 {
    struct mp_config_table *mc;
@@ -79,6 +91,12 @@ static void *smp_write_config_table(void *v)
    	outb(intr_data[byte], 0xC01);
    }

+	/* program the SB800 PIC mode interrupt routing register values */
+	for (byte = 0x0; byte < sizeof(intr_data_pic); byte++) {
+		outb(byte, 0xC00);
+		outb(intr_data_pic[byte], 0xC01);
+	}
+
    /* I/O Ints:    Type    Polarity        Trigger  Bus ID  IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
    smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -153,6 +171,25 @@ static void *smp_write_config_table(void *v)
    IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
    /* There is no extension information... */

+	/* program interrupt line registers for legacy OS use */
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x01, 0)), 0x3C, 0x0B);
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x01, 1)), 0x3C, 0x0A);
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x04, 0)), 0x3C, 0x0B);
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x11, 0)), 0x3C, 0x0A);
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x12, 0)), 0x3C, 0x0B);
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x12, 2)), 0x3C, 0x0A);
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x13, 0)), 0x3C, 0x0B);
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x13, 2)), 0x3C, 0x0A);
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x14, 1)), 0x3C, 0x0A);
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x14, 2)), 0x3C, 0x0B);
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x14, 5)), 0x3C, 0x0B);
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x16, 0)), 0x3C, 0x0B);
+	pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x16, 2)), 0x3C, 0x0A);
+	pci_write_config32(dev_find_slot(3, PCI_DEVFN(0x00, 0)), 0x3C, 0x0B);
+
+	/* program slave PIC edge-level control register */
+	outb(0x0C, 0x4D1);
+
    /* Compute the checksums */
    return mptable_finalize(mc);
 }