Change in coreboot[master]: soc/amd/common/block/espi_util: Workaround in-band reset race condition

[Furquan Shaikh (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54070 )

Change subject: soc/amd/common/block/espi_util: Workaround in-band reset race condition
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Patch Set 2:

(1 comment)

File src/soc/amd/common/block/lpc/espi_util.c:

https://review.coreboot.org/c/coreboot/+/54070/comment/ec63e77b_390f7ce2 
PS1, Line 558: workaround
> A port 80 write in the middle of espi_setup is another race condition.

I think we are going to have to ensure that there is always a single owner that is driving transactions on the eSPI bus. As soon as PSP hands over to x86, there must not be any further usage of eSPI bus by the PSP. This is otherwise going to lead to all kinds of problems at runtime. (The above suggestion about eSPI_RESET# won't really help in this case. It is just something that will have to be addressed in PSP firmware).