Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29301 )
Change subject: src: Use include <reset.h> when appropriate ......................................................................
src: Use include <reset.h> when appropriate
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/arch/x86/cf9_reset.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/cpu/intel/fsp_model_406dx/bootblock.c M src/drivers/intel/fsp2_0/stage_cache.c M src/ec/google/chromeec/ec.c M src/lib/hardwaremain.c M src/mainboard/google/foster/pmic.c M src/mainboard/google/smaug/pmic.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_rialto/bootblock.c M src/security/tpm/tspi/tspi.c M src/security/vboot/common.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c M src/soc/intel/skylake/romstage/romstage.c M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/sb700/early_setup.c M src/southbridge/nvidia/ck804/early_setup_car.c 22 files changed, 6 insertions(+), 21 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c index c28e448..d1e5704 100644 --- a/src/arch/x86/cf9_reset.c +++ b/src/arch/x86/cf9_reset.c @@ -18,7 +18,6 @@ #include <cf9_reset.h> #include <console/console.h> #include <halt.h> -#include <reset.h>
/* * A system reset in terms of the CF9 register asserts the INIT# diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h index 65649d6..d09fc82 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.h +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.h @@ -22,7 +22,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> #include <cpu/amd/multicore.h> -#include <reset.h> #include <northbridge/amd/amdfam10/raminit.h> #include "defaults.h"
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 2ffbd8b..14cfad9 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -21,7 +21,6 @@ #include <cpu/x86/mtrr.h> #include <arch/io.h> #include <device/pci_ops.h> -#include <reset.h> #include <southbridge/intel/fsp_rangeley/soc.h>
#include "model_406dx.h" diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c index 434eae9..a9ec154 100644 --- a/src/drivers/intel/fsp2_0/stage_cache.c +++ b/src/drivers/intel/fsp2_0/stage_cache.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <fsp/memmap.h> #include <stage_cache.h> -#include <reset.h> #include <program_loading.h>
void stage_cache_external_region(void **base, size_t *size) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 57c1b58..5a2630e 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -23,7 +23,6 @@ #include <bootstate.h> #include <delay.h> #include <elog.h> -#include <reset.h> #include <rtc.h> #include <stdlib.h> #include <security/vboot/vboot_common.h> diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 493ff2d..2881162 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -29,7 +29,6 @@ #include <device/pci.h> #include <delay.h> #include <stdlib.h> -#include <reset.h> #include <boot/tables.h> #include <program_loading.h> #if CONFIG(HAVE_ACPI_RESUME) diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index 8d4f855..e3efd34 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -18,11 +18,11 @@ #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> +#include <reset.h> #include <stdint.h> #include <stdlib.h>
#include "pmic.h" -#include "reset.h"
enum { MAX77620_I2C_ADDR = 0x3c diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 75075ad..d9dacb7 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -18,11 +18,11 @@ #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> +#include <reset.h> #include <stdint.h> #include <stdlib.h>
#include "pmic.h" -#include "reset.h"
enum { MAX77620_I2C_ADDR = 0x3c, diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c index 86834bf..80fe7e8 100644 --- a/src/mainboard/google/veyron/bootblock.c +++ b/src/mainboard/google/veyron/bootblock.c @@ -18,7 +18,6 @@ #include <assert.h> #include <bootblock_common.h> #include <delay.h> -#include <reset.h> #include <soc/clock.h> #include <soc/i2c.h> #include <soc/grf.h> diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c index 18047f2..1107b1a 100644 --- a/src/mainboard/google/veyron_mickey/bootblock.c +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -18,7 +18,6 @@ #include <assert.h> #include <bootblock_common.h> #include <delay.h> -#include <reset.h> #include <soc/clock.h> #include <soc/i2c.h> #include <soc/grf.h> diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index 73f57d1..91396b0 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -18,7 +18,6 @@ #include <assert.h> #include <bootblock_common.h> #include <delay.h> -#include <reset.h> #include <soc/clock.h> #include <soc/i2c.h> #include <soc/grf.h> diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index d789278..e466eb8 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -17,7 +17,6 @@
#include <console/cbmem_console.h> #include <console/console.h> -#include <reset.h> #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <stdlib.h> diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 5b49ebf..8f8165a 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -16,7 +16,6 @@ #include <assert.h> #include <cbmem.h> #include <console/console.h> -#include <reset.h> #include <stdint.h> #include <string.h> #include <symbols.h> diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c index 066155e..f8fa8d4 100644 --- a/src/soc/cavium/common/bdk-coreboot.c +++ b/src/soc/cavium/common/bdk-coreboot.c @@ -22,7 +22,6 @@ #include <device/i2c_simple.h> #include <endian.h> #include <delay.h> -#include <reset.h> #include <soc/timer.h>
// BDK diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index ca1eb40..ae2eac8 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -31,7 +31,6 @@ #include <mrc_cache.h> #include <string.h> #include <timestamp.h> -#include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> #include <fsp/util.h> #include <soc/gpio.h> diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 61ad7ed..9dbfbd4 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -24,7 +24,6 @@ #include <delay.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> -#include <reset.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pm.h> diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index b471e5c..5351a01 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -27,7 +27,6 @@ #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/gpio.h> -#include <reset.h>
/* * check for a warm reset and do a hard reset instead. diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index ac43c27..d8188f6 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -26,7 +26,6 @@ #include <elog.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pmclib.h> -#include <reset.h> #include <soc/pci_devs.h> #include <soc/pei_wrapper.h> #include <soc/pm.h> diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index f71f453..c3a4d41 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> -#include <reset.h> + #include "hudson.h"
void hudson_pci_port80(void) diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index abfa897..34a3513 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -22,7 +22,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> -#include <reset.h> + #include "hudson.h" #include "pci_devs.h" #include <Fch/Fch.h> diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 3b801ba..1c24883 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -25,7 +25,6 @@ #include <cpu/x86/msr.h> #include <device/pci.h>
-#include <reset.h> #include "sb700.h" #include "smbus.h"
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index c1670c6..1e357df 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -17,7 +17,9 @@ */
#include <arch/io.h> +#include <reset.h> #include <southbridge/amd/common/reset.h> + #include "ck804.h"
/* Someone messed up and snuck in some K8-specific code */
-
Nico Huber (Code Review)