[M] Change in coreboot[main]: [WIP] mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips

[Felix Held (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81101?usp=email )

Change subject: [WIP] mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips
......................................................................

[WIP] mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips

Add the stub MPIO chips that contain the PCIe engine configuration for
the external PCIe interfaces to the devicetree. Birman's
port_descriptors_phoenix.c was used as a reference. The static
configuration in the devicetree assumes that the default WLAN0_WWAN0 is
selected; for the other cases we'll still need to fix up things
accordingly in the mutable devicetree. Since the chip_info and chip_ops
get assigned to the devices below the chip, a generic dummy device is
added for each chip. In order for the runtime power management of the
NVMe SSDs to work, the NVMe PCIe devices behind external PCIe port
bridges need to be below a drivers/pcie/rtd3/device chip entry. Those
chips and devices below the bridges to the external PCIe ports are
independent of each other; the MPIO chip has the info used for the MPIO
lane and engine configuration for the PCIe port on the host side while
the rtd3 chip has the info that gets attached to the device behind that
bridge.

[TODO] Still need to figure out which value needs to be assigned to the
gpio_group struct element. I'd expect this to be GPIO_26, but still need
to verify this. Also the WLAN01 and WWAN01 cases need to be handled, but
that's probably something for a follow-up patch.

Signed-off-by: Felix Held 
Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb
---
M src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
1 file changed, 63 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/81101/1

diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
index 58cead5..aaccc8b 100644
--- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
+++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb
@@ -44,7 +44,25 @@
    device domain 0 on
    	device ref iommu on end
    	device ref gpp_bridge_1_1 on end # MXM
+			chip vendorcode/amd/opensil/stub/mpio
+				register "type" = "ENGINE_PCIE"
+				register "start_lane" = "0"
+				register "end_lane" = "7"
+				register "gpio_group" = "1" # TODO
+				register "aspm" = "ASPM_L1"
+				register "clk_req" = "CLK_REQ0"
+				device generic 0 on end # dummy for configuring mpio
+			end
    	device ref gpp_bridge_1_2 on
+			chip vendorcode/amd/opensil/stub/mpio
+				register "type" = "ENGINE_PCIE"
+				register "start_lane" = "8"
+				register "end_lane" = "11"
+				register "gpio_group" = "1" # TODO
+				register "aspm" = "ASPM_L1"
+				register "clk_req" = "CLK_REQ1"
+				device generic 0 on end
+			end
    		# Required so the NVMe gets placed into D3 when entering S0i3.
    		chip drivers/pcie/rtd3/device
    			register "name" = ""NVME""
@@ -52,10 +70,55 @@
    		end
    	end # NVMe SSD1
    	device ref gpp_bridge_1_3 on end # GBE
+			chip vendorcode/amd/opensil/stub/mpio
+				register "type" = "ENGINE_PCIE"
+				register "start_lane" = "12"
+				register "end_lane" = "12"
+				register "gpio_group" = "1" # TODO
+				register "aspm" = "ASPM_DISABLED"
+				register "clk_req" = "CLK_REQ6"
+				device generic 0 on end
+			end
    	device ref gpp_bridge_2_1 on end # SD
+			chip vendorcode/amd/opensil/stub/mpio
+				register "type" = "ENGINE_PCIE"
+				register "start_lane" = "13"
+				register "end_lane" = "13"
+				register "gpio_group" = "1" # TODO
+				register "aspm" = "ASPM_DISABLED"
+				register "clk_req" = "CLK_REQ5"
+				device generic 0 on end
+			end
    	device ref gpp_bridge_2_2 on end # WWAN
+			chip vendorcode/amd/opensil/stub/mpio
+				register "type" = "ENGINE_PCIE"
+				register "start_lane" = "14"
+				register "end_lane" = "14"
+				register "gpio_group" = "1" # TODO
+				register "aspm" = "ASPM_DISABLED"
+				register "clk_req" = "CLK_REQ4"
+				device generic 0 on end
+			end
    	device ref gpp_bridge_2_3 on end # WIFI
+			chip vendorcode/amd/opensil/stub/mpio
+				register "type" = "ENGINE_PCIE"
+				register "start_lane" = "15"
+				register "end_lane" = "15"
+				register "gpio_group" = "1" # TODO
+				register "aspm" = "ASPM_DISABLED"
+				register "clk_req" = "CLK_REQ3"
+				device generic 0 on end
+			end
    	device ref gpp_bridge_2_4 on
+			chip vendorcode/amd/opensil/stub/mpio
+				register "type" = "ENGINE_PCIE"
+				register "start_lane" = "16"
+				register "end_lane" = "19"
+				register "gpio_group" = "1" # TODO
+				register "aspm" = "ASPM_DISABLED"
+				register "clk_req" = "CLK_REQ2"
+				device generic 0 on end
+			end
    		# Required so the NVMe gets placed into D3 when entering S0i3.
    		chip drivers/pcie/rtd3/device
    			register "name" = ""NVME""