Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17693
-gerrit
commit e810bd9f7929abf59e85925f425decaaed0d9bc5 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Thu Dec 1 22:08:18 2016 +0200
PCI ops: MMCONF_SUPPORT_DEFAULT is permanent choice
Doing PCI config operations via MMIO window is here to stay and we do not support the option of making it disabled.
Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/Kconfig | 9 --------- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/include/arch/pci_io_cfg.h | 2 +- src/arch/x86/include/arch/pci_mmio_cfg.h | 8 ++++---- src/arch/x86/include/arch/pci_ops.h | 3 --- src/device/Kconfig | 17 ++++++++++++----- src/device/pci_ops.c | 7 +++---- src/mainboard/google/beltino/Kconfig | 1 - src/northbridge/amd/amdfam10/northbridge.c | 25 ++++++++++++------------- src/northbridge/amd/pi/00630F01/northbridge.c | 3 +-- src/northbridge/amd/pi/00660F01/northbridge.c | 3 +-- src/northbridge/amd/pi/00670F00/northbridge.c | 3 +-- src/northbridge/amd/pi/00730F01/northbridge.c | 3 +-- src/northbridge/via/vx900/early_vx900.c | 3 +-- src/southbridge/intel/i82801gx/i82801gx.c | 4 ---- src/southbridge/intel/i82801ix/i82801ix.c | 4 ---- 16 files changed, 38 insertions(+), 59 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig index 5cd0254..a22a2b3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -550,15 +550,6 @@ config MAX_CPUS int default 1
-config MMCONF_SUPPORT_DEFAULT - bool - default n - -config MMCONF_SUPPORT - bool - default y if MMCONF_SUPPORT_DEFAULT - default n - source "src/console/Kconfig"
config HAVE_ACPI_RESUME diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c4bb1cc..848e32c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -332,7 +332,7 @@ ramstage-y += memset.c ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-y += pci_ops_conf1.c -ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c +ramstage-$(CONFIG_MMCONF_SUPPORT_DEFAULT) += pci_ops_mmconf.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-y += tables.c diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index b838535..47f7067 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -94,7 +94,7 @@ void pci_io_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) outl(value, 0xCFC); }
-#if !CONFIG_MMCONF_SUPPORT_DEFAULT +#if IS_ENABLED(CONFIG_NO_MMCONF_SUPPORT) #define pci_read_config8 pci_io_read_config8 #define pci_read_config16 pci_io_read_config16 #define pci_read_config32 pci_io_read_config32 diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index 8caff5a..65cc7be 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -18,7 +18,8 @@
#include <arch/io.h>
-#if CONFIG_MMCONF_SUPPORT +#if IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT) + #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
static inline __attribute__ ((always_inline)) @@ -69,7 +70,6 @@ void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value) write32(addr, value); }
-#if CONFIG_MMCONF_SUPPORT_DEFAULT #define pci_read_config8 pci_mmio_read_config8 #define pci_read_config16 pci_mmio_read_config16 #define pci_read_config32 pci_mmio_read_config32 @@ -77,7 +77,7 @@ void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value) #define pci_write_config8 pci_mmio_write_config8 #define pci_write_config16 pci_mmio_write_config16 #define pci_write_config32 pci_mmio_write_config32 -#endif
-#endif /* CONFIG_MMCONF_SUPPORT */ +#endif /* CONFIG_MMCONF_SUPPORT_DEFAULT */ + #endif /* _PCI_MMIO_CFG_H */ diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index b662170..1b245aa 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -17,10 +17,7 @@ #ifndef __SIMPLE_DEVICE__
extern const struct pci_bus_operations pci_cf8_conf1; - -#if CONFIG_MMCONF_SUPPORT extern const struct pci_bus_operations pci_ops_mmconf; -#endif
const struct pci_bus_operations *pci_bus_default_ops(device_t dev);
diff --git a/src/device/Kconfig b/src/device/Kconfig index fb0aaba..693dfc5 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -217,31 +217,38 @@ config PCI bool default n
+if PCI + +config NO_MMCONF_SUPPORT + bool + default !MMCONF_SUPPORT_DEFAULT + +config MMCONF_SUPPORT_DEFAULT + bool + default n + config HYPERTRANSPORT_PLUGIN_SUPPORT bool - depends on PCI default n
config PCIX_PLUGIN_SUPPORT bool - depends on PCI default y
config CARDBUS_PLUGIN_SUPPORT bool - depends on PCI default y
config AZALIA_PLUGIN_SUPPORT bool - depends on PCI default n
config PCIEXP_PLUGIN_SUPPORT bool - depends on PCI default y
+endif # PCI + if PCIEXP_PLUGIN_SUPPORT
config PCIEXP_COMMON_CLOCK diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 2f896d2..b6fc32d 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -22,11 +22,10 @@
const struct pci_bus_operations *pci_bus_default_ops(device_t dev) { -#if CONFIG_MMCONF_SUPPORT_DEFAULT + if (IS_ENABLED(CONFIG_NO_MMCONF_SUPPORT)) + return &pci_cf8_conf1; + return &pci_ops_mmconf; -#else - return &pci_cf8_conf1; -#endif }
static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, struct device *dev) diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 608523e..c430018 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -9,7 +9,6 @@ config BOARD_GOOGLE_BASEBOARD_BELTINO select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 5634441..605db3a 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -740,19 +740,18 @@ static void amdfam10_domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
- if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) { - struct resource *res = new_resource(dev, 0xc0010058); - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ - res->align = log2(res->size); - res->gran = log2(res->size); - res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ - ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); - } + /* We have MMCONF_SUPPORT_DEFAULT, create the resource window. */ + struct resource *res = new_resource(dev, 0xc0010058); + res->base = CONFIG_MMCONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ + ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);
if (is_fam15h()) { enable_cc6 = 0; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index fb115ff..4872db0 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -335,8 +335,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) - enable_mmconf_resource(dev); + enable_mmconf_resource(dev); }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 115d760..4c1254c 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -330,8 +330,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) - enable_mmconf_resource(dev); + enable_mmconf_resource(dev); }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index ce0dde3..9a39410 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -330,8 +330,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) - enable_mmconf_resource(dev); + enable_mmconf_resource(dev); }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 5b83721..44f91e2 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -338,8 +338,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) - enable_mmconf_resource(dev); + enable_mmconf_resource(dev); }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index eb5c79c..6e1bc23 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -40,14 +40,13 @@ void vx900_enable_pci_config_space(void) * accessed */ pci_io_write_config8(HOST_CTR, 0x4f, 0x01);
-#if CONFIG_MMCONF_SUPPORT /* COOL, now enable MMCONF */ u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60); reg8 |= 3; pci_io_write_config8(TRAF_CTR, 0x60, reg8); + reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28; pci_io_write_config8(TRAF_CTR, 0x61, reg8); -#endif }
/** diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 6d97088..aab674b 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -20,10 +20,6 @@ #include "i82801gx.h" #include "sata.h"
-#if !CONFIG_MMCONF_SUPPORT_DEFAULT -#error ICH7 requires CONFIG_MMCONF_SUPPORT_DEFAULT -#endif - void i82801gx_enable(device_t dev) { u32 reg32; diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index f02429a..0f3a08c 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -23,10 +23,6 @@ #include <console/console.h> #include "i82801ix.h"
-#if !CONFIG_MMCONF_SUPPORT_DEFAULT -#error ICH9 requires CONFIG_MMCONF_SUPPORT_DEFAULT -#endif - typedef struct southbridge_intel_i82801ix_config config_t;
static void i82801ix_enable_device(device_t dev)
-
Kyösti Mälkki