Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38069 )
Change subject: mb/asus/p5qc/devicetree.cb: Drop zero values ......................................................................
mb/asus/p5qc/devicetree.cb: Drop zero values
They default to zero already. Moreover, the comment about AHCI mode no longer applies, as it was made the default mode.
Change-Id: Ife99a79df0289c6db87510ed917438bf47b7f6ca Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb 3 files changed, 3 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/38069/1
diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index e2340b9..f697bff 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -37,10 +37,7 @@ chip southbridge/intel/i82801jx # Southbridge register "gpe0_en" = "0x40"
- # Set AHCI mode. - register "sata_port_map" = "0x3f" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" + register "sata_port_map" = "0x3f"
# Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31" diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index ebaaeca..94ef717 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -37,10 +37,7 @@ chip southbridge/intel/i82801jx # Southbridge register "gpe0_en" = "0x40"
- # Set AHCI mode. - register "sata_port_map" = "0x3f" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" + register "sata_port_map" = "0x3f"
# Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31" diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb index 4e27b46..91e45b4 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb @@ -37,10 +37,7 @@ chip southbridge/intel/i82801jx # Southbridge register "gpe0_en" = "0x40"
- # Set AHCI mode. - register "sata_port_map" = "0x3f" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" + register "sata_port_map" = "0x3f"
# Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31"
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38069 )
Change subject: mb/asus/p5qc/devicetree.cb: Drop zero values ......................................................................
Patch Set 1: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38069 )
Change subject: mb/asus/p5qc/devicetree.cb: Drop zero values ......................................................................
mb/asus/p5qc/devicetree.cb: Drop zero values
They default to zero already. Moreover, the comment about AHCI mode no longer applies, as it was made the default mode.
Change-Id: Ife99a79df0289c6db87510ed917438bf47b7f6ca Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38069 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb M src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb 3 files changed, 3 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index e2340b9..f697bff 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -37,10 +37,7 @@ chip southbridge/intel/i82801jx # Southbridge register "gpe0_en" = "0x40"
- # Set AHCI mode. - register "sata_port_map" = "0x3f" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" + register "sata_port_map" = "0x3f"
# Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31" diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index ebaaeca..94ef717 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -37,10 +37,7 @@ chip southbridge/intel/i82801jx # Southbridge register "gpe0_en" = "0x40"
- # Set AHCI mode. - register "sata_port_map" = "0x3f" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" + register "sata_port_map" = "0x3f"
# Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31" diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb index 4e27b46..91e45b4 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb @@ -37,10 +37,7 @@ chip southbridge/intel/i82801jx # Southbridge register "gpe0_en" = "0x40"
- # Set AHCI mode. - register "sata_port_map" = "0x3f" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" + register "sata_port_map" = "0x3f"
# Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0x31"
-
Angel Pons (Code Review) -
Nico Huber (Code Review)