Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges - coreboot-gerrit

8 Nov 2018


      Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29549 )
Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
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Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/29549/4/src/mainboard/siemens/mc_apl1/varian...
File src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c:
https://review.coreboot.org/#/c/29549/4/src/mainboard/siemens/mc_apl1/varian...
PS4, Line 73: dev->bus->dev->device
So do you need dev->bus->dev->device or dev->device which is used in the upper case?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608
Gerrit-Change-Number: 29549
Gerrit-PatchSet: 4
Gerrit-Owner: Mario Scheithauer mario.scheithauer@siemens.com
Gerrit-Reviewer: Werner Zeh werner.zeh@siemens.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Thu, 08 Nov 2018 15:18:28 +0000
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