Sudheer Amrabadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64886 )
Change subject: common/display: Move mdss configurations to common code base ......................................................................
common/display: Move mdss configurations to common code base
This change makes mdss configuration common for both sc7180 & sc7280 to avoid code duplicacy.
Change-Id: Ibc43ab6ee5ced08e34625e1485febd2f4717d6a0 Signed-off-by: Vinod Polimera quic_vpolimer@quicinc.com --- R src/soc/qualcomm/common/display/mdss.c M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h 3 files changed, 128 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/64886/1
diff --git a/src/soc/qualcomm/sc7180/display/mdss.c b/src/soc/qualcomm/common/display/mdss.c similarity index 70% rename from src/soc/qualcomm/sc7180/display/mdss.c rename to src/soc/qualcomm/common/display/mdss.c index 9569760..0b3a17f 100644 --- a/src/soc/qualcomm/sc7180/display/mdss.c +++ b/src/soc/qualcomm/common/display/mdss.c @@ -2,7 +2,9 @@
#include <device/mmio.h> #include <console/console.h> +#include <delay.h> #include <edid.h> +#include <soc/clock.h> #include <soc/display/mdssreg.h>
#define MDSS_MDP_MAX_PREFILL_FETCH 24 @@ -41,7 +43,7 @@ write32(&mdp_sspp->sspp_src_format, 0x000236ff); write32(&mdp_sspp->sspp_src_unpack_pattern, 0x03020001);
- flip_bits |= BIT(31); + flip_bits |= SW_PIX_EXT_OVERRIDE; write32(&mdp_sspp->sspp_sw_pic_ext_c0_req_pixels, out_size); write32(&mdp_sspp->sspp_sw_pic_ext_c1c2_req_pixels, out_size); write32(&mdp_sspp->sspp_sw_pic_ext_c3_req_pixels, out_size); @@ -56,27 +58,45 @@
static void mdss_intf_tg_setup(struct edid *edid) { - uint32_t hsync_period, vsync_period; - uint32_t hsync_start_x, hsync_end_x; + uint32_t hsync_period, vsync_period, hsync_start_x, hsync_end_x; + uint32_t active_vstart, active_vend, active_hctl; uint32_t display_hctl, hsync_ctl, display_vstart, display_vend; + uint32_t mdss_version;
+ mdss_version = read32(&mdss_hw->hw_version); hsync_period = edid->mode.ha + edid->mode.hbl; vsync_period = edid->mode.va + edid->mode.vbl; - hsync_start_x = edid->mode.hbl - edid->mode.hso; - hsync_end_x = hsync_period - edid->mode.hso - 1; - display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period; - display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - 1; - hsync_ctl = (hsync_period << 16) | edid->mode.hspw; - display_hctl = (hsync_end_x << 16) | hsync_start_x; + + /* SC7280 has mdss version 7.2.0 */ + if (mdss_version == 0x70020000) { + display_vstart = edid->mode.vbl * hsync_period + edid->mode.hbl; + display_vend = (vsync_period * hsync_period) - 1; + hsync_ctl = (hsync_period << 16) | edid->mode.hspw; + display_hctl = edid->mode.hbl | (hsync_period - 1) << 16; + active_vstart = edid->mode.vbl * hsync_period; + active_vend = display_vend; + active_hctl = display_hctl; + + write32(&mdp_intf->intf_active_v_start_f0, active_vstart); + write32(&mdp_intf->intf_active_v_end_f0, active_vend); + write32(&mdp_intf->intf_active_hctl, active_hctl); + write32(&mdp_intf->display_data_hctl, display_hctl); + } else { + hsync_start_x = edid->mode.hbl - edid->mode.hso; + hsync_end_x = hsync_period - edid->mode.hso - 1; + display_vstart = (edid->mode.vbl - edid->mode.vso) * hsync_period; + display_vend = ((vsync_period - edid->mode.vso) * hsync_period) - 1; + hsync_ctl = (hsync_period << 16) | edid->mode.hspw; + display_hctl = (hsync_end_x << 16) | hsync_start_x; + }
write32(&mdp_intf->intf_hsync_ctl, hsync_ctl); - write32(&mdp_intf->intf_vysnc_period_f0, - vsync_period * hsync_period); - write32(&mdp_intf->intf_vysnc_pulse_width_f0, - edid->mode.vspw * hsync_period); + write32(&mdp_intf->intf_vysnc_period_f0, vsync_period * hsync_period); + write32(&mdp_intf->intf_vysnc_pulse_width_f0, edid->mode.vspw * hsync_period); write32(&mdp_intf->intf_disp_hctl, display_hctl); write32(&mdp_intf->intf_disp_v_start_f0, display_vstart); write32(&mdp_intf->intf_disp_v_end_f0, display_vend); + write32(&mdp_intf->display_data_hctl, display_hctl); write32(&mdp_intf->intf_underflow_color, 0x00); write32(&mdp_intf->intf_panel_format, 0x2100); } @@ -85,7 +105,7 @@ { uint32_t v_total, h_total, fetch_start, vfp_start; uint32_t prefetch_avail, prefetch_needed; - uint32_t fetch_enable = BIT(31); + uint32_t fetch_enable = PROG_FETCH_START_EN;
/* * MDP programmable fetch is for MDP with rev >= 1.05. @@ -135,8 +155,8 @@ }
/* Enable border fill */ - left_staging_level = BIT(24); - left_staging_level |= BIT(1); + left_staging_level = BORDER_OUT; + left_staging_level |= VIG_0_OUT;
/* Base layer for layer mixer 0 */ write32(&mdp_ctl->ctl_layer0, left_staging_level); @@ -166,6 +186,9 @@
void mdp_dsi_video_config(struct edid *edid) { + uint32_t mdss_version; + + mdss_version = read32(&mdss_hw->hw_version); mdss_intf_tg_setup(edid); mdss_intf_fetch_start_config(edid); mdss_vbif_setup(); @@ -173,19 +196,39 @@ mdss_source_pipe_config(edid); mdss_layer_mixer_setup(edid);
- /* Select Video Mode Interface */ - write32(&mdp_ctl->ctl_top, 0x0); + if (mdss_version == 0x70020000) { + /* Select vigo pipe active */ + write32(&mdp_ctl->ctl_fetch_pipe_active, FETCH_PIPE_VIG0_ACTIVE);
- /* PPB0 to INTF1 */ - write32(&mdp_ctl->ctl_intf_active, BIT(1)); + /* Select Video Mode Interface */ + write32(&mdp_ctl->ctl_top, 0x0F0000000); + + /* PPB0 to INTF1 */ + write32(&mdp_ctl->ctl_intf_active, INTF_ACTIVE_5); + } else { + /* Select Video Mode Interface */ + write32(&mdp_ctl->ctl_top, 0x0); + + /* PPB0 to INTF1 */ + write32(&mdp_ctl->ctl_intf_active, INTF_ACTIVE_1); + } + write32(&mdp_intf->intf_mux, 0x0F0000); }
void mdp_dsi_video_on(void) { uint32_t ctl0_reg_val; + uint32_t mdss_version; + uint32_t intf_flush; + + mdss_version = read32(&mdss_hw->hw_version); + if (mdss_version == 0x70020000) + intf_flush = INTF_FLUSH_5; + else + intf_flush = INTF_FLUSH_1;
ctl0_reg_val = VIG_0 | LAYER_MIXER_0 | CTL | INTF; - write32(&mdp_ctl->ctl_intf_flush, 0x2); + write32(&mdp_ctl->ctl_intf_flush, intf_flush); write32(&mdp_ctl->ctl_flush, ctl0_reg_val); } diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index c8d7f2f..853c267 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -45,7 +45,7 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/mdss.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/display/mdss.c
################################################################################
diff --git a/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h b/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h index 112cac6..35aa52c 100644 --- a/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h +++ b/src/soc/qualcomm/sc7180/include/soc/display/mdssreg.h @@ -235,7 +235,14 @@ uint32_t intf_active_hctl; uint32_t intf_border_color; uint32_t intf_underflow_color; - uint32_t reserved0[17]; + uint32_t hsync_skew; + uint32_t polarity_ctl; + uint32_t test_ctl; + uint32_t tp_color0; + uint32_t tp_color1; + uint32_t intf_config2; + uint32_t display_data_hctl; + uint32_t reserved0[10]; uint32_t intf_panel_format; uint32_t reserved1[55]; uint32_t intf_prof_fetch_start; @@ -256,7 +263,9 @@ uint32_t ctl_start; uint32_t reserved1[53]; uint32_t ctl_intf_active; - uint32_t reserved2[6]; + uint32_t ctl_cdm_active; + uint32_t ctl_fetch_pipe_active; /* reserved for sc7180 */ + uint32_t reserved2[4]; uint32_t ctl_intf_flush; };
@@ -308,6 +317,10 @@ check_member(mdp_sspp_regs, sspp_sw_pic_ext_c1c2_req_pixels, 0x118); check_member(mdp_sspp_regs, sspp_sw_pic_ext_c3_req_pixels, 0x128);
+struct mdss_hw_regs { + uint32_t hw_version; +}; + struct vbif_rt_regs { uint32_t reserved0[88]; uint32_t vbif_out_axi_amemtype_conf0; @@ -448,9 +461,57 @@ BROADCAST_EN = BIT(31), };
+/* MDP_VP_0_VIG_0_SSPP_SRC_OP_MODE */ +enum { + BWC_DEC_EN = BIT(0), + SW_PIX_EXT_OVERRIDE = BIT(31), + +}; + +/* MDP_INTF_x_INTF_CONFIG */ +enum { + INTERLACE_MODE = BIT(0), + REPEAT_PIXEL = BIT(1), + INTERLACE_INIT_SEL = BIT(2), + BORDER_ENABLE = BIT(3), + EDP_PSR_OVERRIDE_EN = BIT(7), + PACK_ALIGN = BIT(10), + DSI_VIDEO_STOP_MODE = BIT(23), + ACTIVE_H_EN = BIT(29), + ACTIVE_V_EN = BIT(30), + PROG_FETCH_START_EN = BIT(31), +}; + +/* MDP_CTL_0_LAYER_0 */ +enum { + VIG_0_OUT = BIT(0), + BORDER_OUT = BIT(24), +}; + +/* MDP_CTL_0_FETCH_PIPE_ACTIVE */ +enum { + FETCH_PIPE_VIG0_ACTIVE = BIT(16), + FETCH_PIPE_VIG1_ACTIVE = BIT(17), +}; + +/* MDP_CTL_0_INTF_ACTIVE*/ +enum { + INTF_ACTIVE_0 = BIT(0), + INTF_ACTIVE_1 = BIT(1), + INTF_ACTIVE_5 = BIT(5), +}; + +/* MDP_CTL_0_INTF_FLUSH */ +enum { + INTF_FLUSH_0 = BIT(0), + INTF_FLUSH_1 = BIT(1), + INTF_FLUSH_5 = BIT(5), +}; + static struct dsi_regs *const dsi0 = (void *)DSI0_CTL_BASE; static struct dsi_phy_regs *const dsi0_phy = (void *)DSI0_PHY_BASE; static struct dsi_phy_pll_qlink_regs *const phy_pll_qlink = (void *)DSI0_PHY_PLL_QLINK_COM; +static struct mdss_hw_regs *const mdss_hw = (void *)MDSS_BASE; static struct mdp_intf_regs *const mdp_intf = (void *)MDP_1_INTF_BASE; static struct mdp_ctl_regs *const mdp_ctl = (void *)MDP_0_CTL_BASE; static struct mdp_layer_mixer_regs *const mdp_layer_mixer = (void *)MDP_VP_0_LAYER_MIXER_BASE;