Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47965 )
Change subject: arch/x86: Link gdt_init.S into bootblock ......................................................................
arch/x86: Link gdt_init.S into bootblock
Followup work forces gdtptr and gdt towards the top of bootblock. They need to be realmode-addressable, i.e. within top 64 KiB or same segment with .reset.
Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/Makefile.inc M src/arch/x86/c_start.S M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/32bit/entry32.inc 4 files changed, 4 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47965/1
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 5157564..00917f0 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -98,6 +98,7 @@ bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c +bootblock-y += gdt_init.S bootblock-y += id.S bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
@@ -160,8 +161,6 @@
romstage-y += boot.c romstage-y += post.c -# gdt_init.S is included by entry32.inc when romstage is the first C -# environment. romstage-y += gdt_init.S romstage-y += cpu_common.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index a7af64f..8bebf87 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -142,10 +142,10 @@
/* This is the gdt for GCC part of coreboot. * It is different from the gdt in ASM part of coreboot - * which is defined in entry32.inc + * which is defined in gdt_init.S * * When the machine is initially started, we use a very simple - * gdt from ROM (that in entry32.inc) which only contains those + * gdt from ROM (that in gdt_init.S) which only contains those * entries we need for protected mode. * * When we're executing code from RAM, we want to do more complex diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 2665cc6..5e90da1 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -124,7 +124,7 @@ ljmpl $ROM_CODE_SEG, $__protected_start
/** - * The gdt is defined in entry32.inc, it has a 4 Gb code segment + * The gdt is defined in gdt_init.S, it has a 4 Gb code segment * at 0x08, and a 4 GB data segment at 0x10; */ __gdtptr: diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 8509448..873a809 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -4,7 +4,6 @@
#include <arch/rom_segs.h> #include <cpu/x86/post_code.h> -#include <arch/x86/gdt_init.S>
.code32 /*
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47965 )
Change subject: arch/x86: Link gdt_init.S into bootblock ......................................................................
Patch Set 1: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47965 )
Change subject: arch/x86: Link gdt_init.S into bootblock ......................................................................
arch/x86: Link gdt_init.S into bootblock
Followup work forces gdtptr and gdt towards the top of bootblock. They need to be realmode-addressable, i.e. within top 64 KiB or same segment with .reset.
Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47965 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/arch/x86/Makefile.inc M src/arch/x86/c_start.S M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/32bit/entry32.inc 4 files changed, 4 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 5157564..00917f0 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -98,6 +98,7 @@ bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c +bootblock-y += gdt_init.S bootblock-y += id.S bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
@@ -160,8 +161,6 @@
romstage-y += boot.c romstage-y += post.c -# gdt_init.S is included by entry32.inc when romstage is the first C -# environment. romstage-y += gdt_init.S romstage-y += cpu_common.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index a7af64f..8bebf87 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -142,10 +142,10 @@
/* This is the gdt for GCC part of coreboot. * It is different from the gdt in ASM part of coreboot - * which is defined in entry32.inc + * which is defined in gdt_init.S * * When the machine is initially started, we use a very simple - * gdt from ROM (that in entry32.inc) which only contains those + * gdt from ROM (that in gdt_init.S) which only contains those * entries we need for protected mode. * * When we're executing code from RAM, we want to do more complex diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 2665cc6..5e90da1 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -124,7 +124,7 @@ ljmpl $ROM_CODE_SEG, $__protected_start
/** - * The gdt is defined in entry32.inc, it has a 4 Gb code segment + * The gdt is defined in gdt_init.S, it has a 4 Gb code segment * at 0x08, and a 4 GB data segment at 0x10; */ __gdtptr: diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 8509448..873a809 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -4,7 +4,6 @@
#include <arch/rom_segs.h> #include <cpu/x86/post_code.h> -#include <arch/x86/gdt_init.S>
.code32 /*