Change in coreboot[master]: vc/amd/fsp/cezanne: update UPD headers

[Felix Held (Code Review)]

Attention is currently required from: Furquan Shaikh, Marshall Dawson, Paul Menzel, Felix Held.
Felix Held has uploaded a new patch set (#10) to the change originally created by Matt Papageorge. ( https://review.coreboot.org/c/coreboot/+/51806 )

Change subject: vc/amd/fsp/cezanne: update UPD headers
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vc/amd/fsp/cezanne: update UPD headers

The UPD header files get generated as part of the FSP build process. For
the initial Cezanne development we took the Picasso UPD data structures
as a starting point. This patch replaces it with the first version of
the Cezanne-specific UPD data structures that is present in version 12
of the internal work-in-progress FSP binary drops.

The serial_port_stride UPD-M field is removed, since the information is
already given by serial_port_use_mmio. The stride is 4 bytes for the
MMIO UART case and 1 byte for the legacy I/O case.

BUG=b:182524631
TEST=NVMe works on google/guybrush when the rest of the patch train is
applied as well.

Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0
Signed-off-by: Matt Papageorge 
Signed-off-by: Felix Held 
---
M src/soc/amd/cezanne/fsp_m_params.c
M src/soc/amd/cezanne/fsp_s_params.c
M src/vendorcode/amd/fsp/cezanne/FspmUpd.h
M src/vendorcode/amd/fsp/cezanne/FspsUpd.h
4 files changed, 109 insertions(+), 101 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/51806/10