Change in ...coreboot[master]: soc/intel/{cannonlake, icelake}: Enable GPIO PM programming in coreboot

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32790

Change subject: soc/intel/{cannonlake, icelake}: Enable GPIO PM programming in coreboot
......................................................................

soc/intel/{cannonlake, icelake}: Enable GPIO PM programming in coreboot

This patch ensures to override FSP default gpio pm programming based
on platform need.

BUG=b:130764684
TEST=Able to build and boot from fixed media on ICL and CML.

Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/icelake/chip.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32790/1

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 1bd34c3..f64aa17 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -176,6 +176,9 @@

/* TODO(furquan): Get rid of this workaround once FSP is fixed. */
    cnl_configure_pads(NULL, 0);
+
+	/* Overriding FSP default GPIO PM programming. */
+	gpio_pm_configure();
 }

static void pci_domain_set_resources(struct device *dev)
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c
index 11d14de..73f003c 100644
--- a/src/soc/intel/icelake/chip.c
+++ b/src/soc/intel/icelake/chip.c
@@ -117,6 +117,9 @@

/* Restore GPIO IRQ polarities back to previous settings. */
    itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
+	/* Overriding FSP default GPIO PM programming. */
+	gpio_pm_configure();
 }

static void pci_domain_set_resources(struct device *dev)

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, V Sowmya, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32790

to look at the new patch set (#3).

Change subject: soc/intel/{cannonlake, icelake}: Enable GPIO PM programming in coreboot
......................................................................

soc/intel/{cannonlake, icelake}: Enable GPIO PM programming in coreboot

This patch ensures to override FSP default gpio pm programming based
on platform need.

BUG=b:130764684
TEST=Able to build and boot from fixed media on ICL and CML.

Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/icelake/chip.c
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32790/3

Change in ...coreboot[master]: soc/intel/cannonlake: Make use of gpio_pm_configure()

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, V Sowmya, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32790

to look at the new patch set (#5).

Change subject: soc/intel/cannonlake: Make use of gpio_pm_configure()
......................................................................

soc/intel/cannonlake: Make use of gpio_pm_configure()

Provide option in chip.h to set dynamic local clock gating
setting.

BUG=b:130764684
TEST=Able to build and boot CML.

Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/gpio.c
M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
4 files changed, 39 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32790/5

Change in ...coreboot[master]: soc/intel/cannonlake: Make use of gpio_pm_configure()

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, V Sowmya, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32790

to look at the new patch set (#6).

Change subject: soc/intel/cannonlake: Make use of gpio_pm_configure()
......................................................................

soc/intel/cannonlake: Make use of gpio_pm_configure()

Provide option in chip.h to set dynamic local clock gating
setting.

BUG=b:130764684
TEST=Able to build and boot CML.

Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/gpio.c
M src/soc/intel/cannonlake/gpio_cnp_h.c
M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
M src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
6 files changed, 59 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32790/6

Change in ...coreboot[master]: soc/intel/cannonlake: Make use of gpio_pm_configure()

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, V Sowmya, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32790

to look at the new patch set (#7).

Change subject: soc/intel/cannonlake: Make use of gpio_pm_configure()
......................................................................

soc/intel/cannonlake: Make use of gpio_pm_configure()

Provide option in chip.h to set dynamic local clock gating
setting.

BUG=b:130764684
TEST=Able to build and boot CML.

Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
M src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
4 files changed, 42 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32790/7

Change in ...coreboot[master]: soc/intel/cannonlake: Make use of gpio_pm_configure()

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32790 )

Change subject: soc/intel/cannonlake: Make use of gpio_pm_configure()
......................................................................

Patch Set 7:

Same changes as ICL required here.

Change in ...coreboot[master]: soc/intel/cannonlake: Make use of gpio_pm_configure()

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, V Sowmya, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32790

to look at the new patch set (#8).

Change subject: soc/intel/cannonlake: Make use of gpio_pm_configure()
......................................................................

soc/intel/cannonlake: Make use of gpio_pm_configure()

Provide option in chip.h to set dynamic local clock gating
setting.

BUG=b:130764684
TEST=Able to build and boot CML.

Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/gpio.c
M src/soc/intel/cannonlake/gpio_cnp_h.c
M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
M src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
6 files changed, 86 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32790/8

Change in ...coreboot[master]: soc/intel/cannonlake: Make use of gpio_pm_configure()

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32790 )

Change subject: soc/intel/cannonlake: Make use of gpio_pm_configure()
......................................................................

Patch Set 8:
> Same changes as ICL required here.

Done

Change in ...coreboot[master]: soc/intel/cannonlake: Make use of gpio_pm_configure()

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32790 )

Change subject: soc/intel/cannonlake: Make use of gpio_pm_configure()
......................................................................

Patch Set 8: Code-Review+2

Change in ...coreboot[master]: soc/intel/cannonlake: Make use of gpio_pm_configure()

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32790 )

Change subject: soc/intel/cannonlake: Make use of gpio_pm_configure()
......................................................................

soc/intel/cannonlake: Make use of gpio_pm_configure()

Provide option in chip.h to set dynamic local clock gating
setting.

BUG=b:130764684
TEST=Able to build and boot CML.

Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32790
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/gpio.c
M src/soc/intel/cannonlake/gpio_cnp_h.c
M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
M src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
6 files changed, 86 insertions(+), 11 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 1bd34c3..faddbd5 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -166,6 +166,27 @@
    gpio_configure_pads(cfg, num_pads);
 }

+/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */
+static void soc_fill_gpio_pm_configuration(void)
+{
+	uint8_t value[TOTAL_GPIO_COMM];
+	const struct device *dev;
+	dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0);
+	if (!dev || !dev->chip_info)
+		return;
+
+	const config_t *config = dev->chip_info;
+
+	if (config->gpio_override_pm)
+		memcpy(value, config->gpio_pm, sizeof(uint8_t) *
+			TOTAL_GPIO_COMM);
+	else
+		memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+			TOTAL_GPIO_COMM);
+
+	gpio_pm_configure(value, TOTAL_GPIO_COMM);
+}
+
 void soc_init_pre_device(void *chip_info)
 {
    /* Perform silicon specific init. */
@@ -176,6 +197,8 @@

/* TODO(furquan): Get rid of this workaround once FSP is fixed. */
    cnl_configure_pads(NULL, 0);
+
+	soc_fill_gpio_pm_configuration();
 }

static void pci_domain_set_resources(struct device *dev)
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2b2a51f..0d51c1c 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -20,6 +20,7 @@

#include <intelblocks/chip.h>
 #include <drivers/i2c/designware/dw_i2c.h>
+#include <intelblocks/gpio.h>
 #include <intelblocks/gspi.h>
 #include <smbios.h>
 #include <stdint.h>
@@ -402,6 +403,24 @@
    /* Enable GBE wakeup */
    uint8_t LanWakeFromDeepSx;
    uint8_t WolEnableOverride;
+
+	/*
+	 * Override GPIO PM configuration:
+	 * 0: Use FSP default GPIO PM program,
+	 * 1: coreboot to override GPIO PM program
+	 */
+	uint8_t gpio_override_pm;
+	/*
+	 * GPIO PM configuration: 0 to disable, 1 to enable power gating
+	 * Bit 6-7: Reserved
+	 * Bit 5: MISCCFG_GPSIDEDPCGEN
+	 * Bit 4: MISCCFG_GPRCOMPCDLCGEN
+	 * Bit 3: MISCCFG_GPRTCDLCGEN
+	 * Bit 2: MISCCFG_GSXLCGEN
+	 * Bit 1: MISCCFG_GPDPCGEN
+	 * Bit 0: MISCCFG_GPDLCGEN
+	 */
+	uint8_t gpio_pm[TOTAL_GPIO_COMM];
 };

typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c
index dd51464..4036fdc 100644
--- a/src/soc/intel/cannonlake/gpio.c
+++ b/src/soc/intel/cannonlake/gpio.c
@@ -77,8 +77,9 @@
    INTEL_GPP(GPP_C0, GPIO_RSVD_22, GPIO_RSVD_27),		/* HVMOS */
 };

-static const struct pad_community cnl_communities[] = {
-	{ /* GPP A, B, G, SPI */
+static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
+	/* GPP A, B, G, SPI */
+	[COMM_0] = {
    	.port = PID_GPIOCOM0,
    	.first_pad = GPP_A0,
    	.last_pad = GPIO_RSVD_11,
@@ -96,7 +97,9 @@
    	.num_reset_vals = ARRAY_SIZE(rst_map_com0),
    	.groups = cnl_community0_groups,
    	.num_groups = ARRAY_SIZE(cnl_community0_groups),
-	}, { /* GPP D, F, H, VGPIO */
+	},
+	/* GPP D, F, H, VGPIO */
+	[COMM_1] = {
    	.port = PID_GPIOCOM1,
    	.first_pad = GPP_D0,
    	.last_pad = vSD3_CD_B,
@@ -114,7 +117,9 @@
    	.num_reset_vals = ARRAY_SIZE(rst_map),
    	.groups = cnl_community1_groups,
    	.num_groups = ARRAY_SIZE(cnl_community1_groups),
-	}, { /* GPD */
+	},
+	/* GPD */
+	[COMM_2] = {
    	.port = PID_GPIOCOM2,
    	.first_pad = GPD0,
    	.last_pad = GPD11,
@@ -132,7 +137,9 @@
    	.num_reset_vals = ARRAY_SIZE(rst_map),
    	.groups = cnl_community2_groups,
    	.num_groups = ARRAY_SIZE(cnl_community2_groups),
-	}, { /* AZA, CPU */
+	},
+	/* AZA, CPU */
+	[COMM_3] = {
    	.port = PID_GPIOCOM3,
    	.first_pad = HDA_BCLK,
    	.last_pad = GPIO_RSVD_38,
@@ -150,7 +157,9 @@
    	.num_reset_vals = ARRAY_SIZE(rst_map),
    	.groups = cnl_community3_groups,
    	.num_groups = ARRAY_SIZE(cnl_community3_groups),
-	}, { /* GPP C, E, JTAG, HVMOS */
+	},
+	/* GPP C, E, JTAG, HVMOS */
+	[COMM_4] = {
    	.port = PID_GPIOCOM4,
    	.first_pad = GPP_C0,
    	.last_pad = GPIO_RSVD_27,
diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c
index 102444a..dd9f433 100644
--- a/src/soc/intel/cannonlake/gpio_cnp_h.c
+++ b/src/soc/intel/cannonlake/gpio_cnp_h.c
@@ -80,7 +80,8 @@
 };

static const struct pad_community cnl_communities[] = {
-	{ /* GPP A, B */
+	/* GPP A, B */
+	[COMM_0] = {
    	.port = PID_GPIOCOM0,
    	.first_pad = GPP_A0,
    	.last_pad = GPIO_RSVD_2,
@@ -98,7 +99,9 @@
    	.num_reset_vals = ARRAY_SIZE(rst_map_com0),
    	.groups = cnl_community0_groups,
    	.num_groups = ARRAY_SIZE(cnl_community0_groups),
-	}, { /* GPP C, D, G */
+	},
+	/* GPP C, D, G */
+	[COMM_1] = {
    	.port = PID_GPIOCOM1,
    	.first_pad = GPP_C0,
    	.last_pad = vSSP2_RXD,
@@ -116,7 +119,9 @@
    	.num_reset_vals = ARRAY_SIZE(rst_map),
    	.groups = cnl_community1_groups,
    	.num_groups = ARRAY_SIZE(cnl_community1_groups),
-	}, { /* GPD */
+	},
+	/* GPD */
+	[COMM_2] = {
    	.port = PID_GPIOCOM2,
    	.first_pad = GPD0,
    	.last_pad = GPD11,
@@ -134,7 +139,9 @@
    	.num_reset_vals = ARRAY_SIZE(rst_map),
    	.groups = cnl_community2_groups,
    	.num_groups = ARRAY_SIZE(cnl_community2_groups),
-	}, { /* GPP K, H, E, F */
+	},
+	/* GPP K, H, E, F */
+	[COMM_3] = {
    	.port = PID_GPIOCOM3,
    	.first_pad = GPP_K0,
    	.last_pad = GPIO_RSVD_19,
@@ -152,7 +159,9 @@
    	.num_reset_vals = ARRAY_SIZE(rst_map),
    	.groups = cnl_community3_groups,
    	.num_groups = ARRAY_SIZE(cnl_community3_groups),
-	}, { /* GPP I, J */
+	},
+	/* GPP I, J */
+	[COMM_4] = {
    	.port = PID_GPIOCOM4,
    	.first_pad = GPIO_RSVD_20,
    	.last_pad = GPP_J11,
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
index 5990144..698bd2a 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
@@ -355,4 +355,12 @@
 #define TOTAL_PADS		275

#define SD_PWR_EN_PIN		GPP_A17
+
+#define COMM_0		0
+#define COMM_1		1
+#define COMM_2		2
+#define COMM_3		3
+#define COMM_4		4
+#define TOTAL_GPIO_COMM	5
+
 #endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
index 1788e78..5176ac7 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
@@ -399,4 +399,11 @@

#define TOTAL_PADS		(GPD11 + 1)

+#define COMM_0		0
+#define COMM_1		1
+#define COMM_2		2
+#define COMM_3		3
+#define COMM_4		4
+#define TOTAL_GPIO_COMM	5
+
 #endif