[S] Change in coreboot[main]: include/device/pci_def.h: Add PCIe SRIOV definitions

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83319?usp=email )

(

19 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: include/device/pci_def.h: Add PCIe SRIOV definitions
......................................................................

include/device/pci_def.h: Add PCIe SRIOV definitions

Add SRIOV related definitions from section 9.3 of PCI Express Base
Specification Revision 6.2.

Change-Id: Ic4bf76b0e3b20e3d04e8264c6530ab4abb95a013
Signed-off-by: Yuchi Chen 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83319
Tested-by: build bot (Jenkins) 
Reviewed-by: Shuo Liu 
---
M src/include/device/pci_def.h
1 file changed, 11 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Shuo Liu: Looks good to me, approved

diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 6d61e6d..6748b35 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -478,6 +478,7 @@
 #define  PCIE_EXT_CAP_LTR_ID		 0x0018
 #define  PCIE_EXT_CAP_RESIZABLE_BAR	 0x0015
 #define  PCIE_EXT_CAP_RCECEA_ID	0x0007
+#define  PCIE_EXT_CAP_SRIOV_ID	0x0010

/* Secondary PCI Express Extended Capability Structure */
 #define PCI_EXP_SEC_CAP_ID	0x19
@@ -580,6 +581,16 @@
 #define PCI_RCECEA_BUSNUM 8

/*
+ * Single Root IO Virtualization
+ * Section 9.3 of PCI Express Base Specification Revision 6.2.
+ */
+#define PCIE_EXT_CAP_SRIOV_TOTAL_VFS	0x0e
+#define PCIE_EXT_CAP_SRIOV_SUPPORTED_PAGE_SIZE	0x1c
+#define PCIE_EXT_CAP_SRIOV_SYSTEM_PAGE_SIZE	0x20
+#define PCIE_EXT_CAP_SRIOV_VF_BAR0	0x24
+#define PCIE_EXT_CAP_SRIOV_VF_BAR5	0x38
+
+/*
  * The PCI interface treats multi-function devices as independent
  * devices.  The slot/function address of each device is encoded
  * in a single byte as follows: