Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47031 )
Change subject: sb/intel/lynxpoint/sata.c: Don't enable Bus Master ......................................................................
sb/intel/lynxpoint/sata.c: Don't enable Bus Master
Bus Master is not required and reference code does not set it.
Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/47031/1
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 4174e1f..d8eb2a8 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -51,9 +51,8 @@
/* SATA configuration */
- /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + /* Enable memory space decoding for ABAR */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
Hello Felix Singer, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47031
to look at the new patch set (#2).
Change subject: sb/intel/lynxpoint/sata.c: Don't enable Bus Master ......................................................................
sb/intel/lynxpoint/sata.c: Don't enable Bus Master
Bus Master is not required and reference code does not set it.
Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/47031/2
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47031 )
Change subject: sb/intel/lynxpoint/sata.c: Don't enable Bus Master ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/47031/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47031/2//COMMIT_MSG@9 PS2, Line 9: Bus Master is not required and reference code does not set it. Did you test it and does it still work?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47031 )
Change subject: sb/intel/lynxpoint/sata.c: Don't enable Bus Master ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47031/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47031/2//COMMIT_MSG@9 PS2, Line 9: Bus Master is not required and reference code does not set it.
Did you test it and does it still work?
Not yet
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47031 )
Change subject: sb/intel/lynxpoint/sata.c: Don't enable Bus Master ......................................................................
Patch Set 2: Code-Review+2
Hello Felix Singer, build bot (Jenkins), Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47031
to look at the new patch set (#6).
Change subject: sb/intel/lynxpoint/sata.c: Don't enable Bus Master ......................................................................
sb/intel/lynxpoint/sata.c: Don't enable Bus Master
Bus Master is not required and reference code does not set it.
Tested on Asrock B85M Pro4, still boots from SATA SSD with TianoCore.
Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/47031/6
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47031 )
Change subject: sb/intel/lynxpoint/sata.c: Don't enable Bus Master ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47031/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47031/2//COMMIT_MSG@9 PS2, Line 9: Bus Master is not required and reference code does not set it.
Not yet
Done
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47031 )
Change subject: sb/intel/lynxpoint/sata.c: Don't enable Bus Master ......................................................................
sb/intel/lynxpoint/sata.c: Don't enable Bus Master
Bus Master is not required and reference code does not set it.
Tested on Asrock B85M Pro4, still boots from SATA SSD with TianoCore.
Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47031 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Singer felixsinger@posteo.net Reviewed-by: Michael Niewöhner foss@mniewoehner.de --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 2 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 510440b..e1a2fa5 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -41,9 +41,8 @@
/* SATA configuration */
- /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + /* Enable memory space decoding for ABAR */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (config->ide_legacy_combined) { printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
-
Angel Pons (Code Review) -
Felix Singer (Code Review)
-
Michael Niewöhner (Code Review)