Change in coreboot[master]: soc/../tigerlake/acpi: add ACPI _DSD table for ISH firmware name

[Li1 Feng (Code Review)]

Li1 Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39480 )

Change subject: soc/../tigerlake/acpi: add ACPI _DSD table for ISH firmware name
......................................................................

soc/../tigerlake/acpi: add ACPI _DSD table for ISH firmware name

BRANCH=none
BUG=b:145946347
TEST=none

Signed-off-by: Hu, Hebo 
Signed-off-by: li feng 
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
---
A src/soc/intel/tigerlake/acpi/ish.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39480/1

diff --git a/src/soc/intel/tigerlake/acpi/ish.asl b/src/soc/intel/tigerlake/acpi/ish.asl
new file mode 100644
index 0000000..186a147
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/ish.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Integrated Sensor Hub Controller 0:12.0 */
+
+Device (ISHB)
+{
+	Name (_ADR, 0x00120000)
+	Name (_DDN, "Integrated Sensor Hub Controller")
+}
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 8593d07..8e17abb 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -46,6 +46,9 @@
 /* SMBus 0:1f.4 */
 #include "smbus.asl"

+/* ISH 0:12.0 */
+#include "ish.asl"
+
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39480 )

Change subject: soc/../tigerlake/acpi: add ACPI _DSD table for ISH firmware name
......................................................................

Patch Set 1: Code-Review+2

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39480 )

Change subject: soc/../tigerlake/acpi: add ACPI _DSD table for ISH firmware name
......................................................................

Patch Set 1: Code-Review+1

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39480 )

Change subject: soc/../tigerlake/acpi: add ACPI _DSD table for ISH firmware name
......................................................................

Patch Set 1:

(1 comment)

Add topic info: TGL_UPSTREAM

https://review.coreboot.org/c/coreboot/+/39480/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39480/1//COMMIT_MSG@11 
PS1, Line 11: TEST=none
Add test information

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39480 )

Change subject: soc/../tigerlake/acpi: add ACPI _DSD table for ISH firmware name
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39480/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39480/1//COMMIT_MSG@7 
PS1, Line 7: soc/../tigerlake/acpi
soc/intel/tigerlake:

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39480 )

Change subject: soc/../tigerlake/acpi: add ACPI _DSD table for ISH firmware name
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39480/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39480/1//COMMIT_MSG@7 
PS1, Line 7: add
Add

Change in coreboot[master]: TGL_UPSTREAM: soc/intel/tigerlake/acpi: Add ACPI _DSD table for ISH f...

[Li1 Feng (Code Review)]

Hello build bot (Jenkins), Wonkyu Kim, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39480

to look at the new patch set (#2).

Change subject: TGL_UPSTREAM: soc/intel/tigerlake/acpi: Add ACPI _DSD table for ISH firmware name
......................................................................

TGL_UPSTREAM: soc/intel/tigerlake/acpi: Add ACPI _DSD table for ISH firmware name

BRANCH=none
BUG=b:145946347
TEST=none

Signed-off-by: Hu, Hebo 
Signed-off-by: li feng 
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
---
A src/soc/intel/tigerlake/acpi/ish.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39480/2

Change in coreboot[master]: TGL_UPSTREAM: soc/intel/tigerlake/acpi: Add ACPI _DSD table for ISH f...

[Li1 Feng (Code Review)]

Li1 Feng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39480 )

Change subject: TGL_UPSTREAM: soc/intel/tigerlake/acpi: Add ACPI _DSD table for ISH firmware name
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39480/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39480/1//COMMIT_MSG@7 
PS1, Line 7: soc/../tigerlake/acpi
> soc/intel/tigerlake:

Done

https://review.coreboot.org/c/coreboot/+/39480/1//COMMIT_MSG@7 
PS1, Line 7: add
> Add

Done

Change in coreboot[master]: TGL_UPSTREAM: soc/intel/tigerlake: Add ACPI _DSD table for ISH firmwa...

[Li1 Feng (Code Review)]

Hello build bot (Jenkins), Wonkyu Kim, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39480

to look at the new patch set (#3).

Change subject: TGL_UPSTREAM: soc/intel/tigerlake: Add ACPI _DSD table for ISH firmware name
......................................................................

TGL_UPSTREAM: soc/intel/tigerlake: Add ACPI _DSD table for ISH firmware name

BRANCH=none
BUG=b:145946347
TEST=none

Signed-off-by: Hu, Hebo 
Signed-off-by: li feng 
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
---
A src/soc/intel/tigerlake/acpi/ish.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39480/3

Change in coreboot[master]: soc/intel/tigerlake: Add ACPI _DSD table for ISH firmware name

[Li1 Feng (Code Review)]

Hello build bot (Jenkins), Wonkyu Kim, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39480

to look at the new patch set (#4).

Change subject: soc/intel/tigerlake: Add ACPI _DSD table for ISH firmware name
......................................................................

soc/intel/tigerlake: Add ACPI _DSD table for ISH firmware name

BRANCH=none
BUG=b:145946347
TEST=none

Signed-off-by: Hu, Hebo 
Signed-off-by: li feng 
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
---
A src/soc/intel/tigerlake/acpi/ish.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39480/4

Change in coreboot[master]: soc/intel/tigerlake: Support ISH

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded a new patch set (#5) to the change originally created by Li1 Feng. ( https://review.coreboot.org/c/coreboot/+/39480 )

Change subject: soc/intel/tigerlake: Support ISH
......................................................................

soc/intel/tigerlake: Support ISH

Add ACPI Object for ISH SSDT
Enable/disable ISH based on devicetree

BRANCH=none
BUG=b:145946347
TEST=none

Signed-off-by: Hu, Hebo 
Signed-off-by: li feng 
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
---
A src/soc/intel/tigerlake/acpi/ish.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
M src/soc/intel/tigerlake/chip.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
4 files changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39480/5

Change in coreboot[master]: soc/intel/tigerlake: Support ISH

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39480 )

Change subject: soc/intel/tigerlake: Support ISH
......................................................................

Patch Set 5: Code-Review+1

Change in coreboot[master]: soc/intel/tigerlake: Support ISH

[Li1 Feng (Code Review)]

Hello build bot (Jenkins), Wonkyu Kim, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39480

to look at the new patch set (#6).

Change subject: soc/intel/tigerlake: Support ISH
......................................................................

soc/intel/tigerlake: Support ISH

Add ACPI Object for ISH SSDT
Enable/disable ISH based on devicetree

BRANCH=none
BUG=b:145946347
TEST=build successfully and boot to OS with TGLRVP UP3

Signed-off-by: Hu, Hebo 
Signed-off-by: li feng 
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
---
A src/soc/intel/tigerlake/acpi/ish.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
M src/soc/intel/tigerlake/chip.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
4 files changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39480/6

Change in coreboot[master]: soc/intel/tigerlake: Support ISH

[Li1 Feng (Code Review)]

Hello build bot (Jenkins), Wonkyu Kim, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39480

to look at the new patch set (#7).

Change subject: soc/intel/tigerlake: Support ISH
......................................................................

soc/intel/tigerlake: Support ISH

Add ACPI Object for ISH SSDT
Enable/disable ISH based on devicetree

BRANCH=none
BUG=b:145946347
TEST=boot to OS with TGL RVP UP3

Signed-off-by: Hu, Hebo 
Signed-off-by: li feng 
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
---
A src/soc/intel/tigerlake/acpi/ish.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
M src/soc/intel/tigerlake/chip.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
4 files changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39480/7

Change in coreboot[master]: soc/intel/tigerlake: Support ISH

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39480 )

Change subject: soc/intel/tigerlake: Support ISH
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39480/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39480/1//COMMIT_MSG@11 
PS1, Line 11: TEST=none
> Add test information

Done

Change in coreboot[master]: soc/intel/tigerlake: Support ISH

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39480 )

Change subject: soc/intel/tigerlake: Support ISH
......................................................................

Patch Set 7: Code-Review+2

Change in coreboot[master]: soc/intel/tigerlake: Support ISH

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39480 )

Change subject: soc/intel/tigerlake: Support ISH
......................................................................

soc/intel/tigerlake: Support ISH

Add ACPI Object for ISH SSDT
Enable/disable ISH based on devicetree

BRANCH=none
BUG=b:145946347
TEST=boot to OS with TGL RVP UP3

Signed-off-by: Hu, Hebo 
Signed-off-by: li feng 
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480
Tested-by: build bot (Jenkins) 
Reviewed-by: Wonkyu Kim 
---
A src/soc/intel/tigerlake/acpi/ish.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
M src/soc/intel/tigerlake/chip.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
4 files changed, 33 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Wonkyu Kim: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/acpi/ish.asl b/src/soc/intel/tigerlake/acpi/ish.asl
new file mode 100644
index 0000000..186a147
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/ish.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Integrated Sensor Hub Controller 0:12.0 */
+
+Device (ISHB)
+{
+	Name (_ADR, 0x00120000)
+	Name (_DDN, "Integrated Sensor Hub Controller")
+}
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 9d25a73..1403eb4 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -49,6 +49,9 @@
 /* SMBus 0:1f.4 */
 #include "smbus.asl"

+/* ISH 0:12.0 */
+#include "ish.asl"
+
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"

diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index 6f6e153..dc36da3 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -71,6 +71,7 @@

switch (dev->path.pci.devfn) {
    case SA_DEVFN_ROOT:	return "MCHC";
+	case PCH_DEVFN_ISH:	return "ISHB";
    case PCH_DEVFN_XHCI:	return "XHCI";
    case PCH_DEVFN_I2C0:	return "I2C0";
    case PCH_DEVFN_I2C1:	return "I2C1";
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index c5629a5..b46f3a3 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -89,6 +89,13 @@
    else
    	m_cfg->InternalGfx = 0x1;

+	/* ISH */
+	dev = pcidev_path_on_root(PCH_DEVFN_ISH);
+	if (!dev || !dev->enabled)
+		m_cfg->PchIshEnable = 0;
+	else
+		m_cfg->PchIshEnable = 1;
+
    /* DP port config */
    m_cfg->DdiPortAConfig = config->DdiPortAConfig;
    m_cfg->DdiPortBConfig = config->DdiPortBConfig;