Change in coreboot[master]: soc/amd/common/blocks: introduce two new BIOSRAM based common blocks
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: soc/amd/common/blocks: introduce two new BIOSRAM based common blocks ......................................................................
soc/amd/common/blocks: introduce two new BIOSRAM based common blocks
All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size.
Create unified BIOSRAM layout, AMD UMA block and AMD RAMTOP block.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da --- A src/soc/amd/common/block/include/amdblocks/biosram_layout.h A src/soc/amd/common/block/include/amdblocks/uma.h A src/soc/amd/common/block/ramtop/Kconfig A src/soc/amd/common/block/ramtop/Makefile.inc A src/soc/amd/common/block/ramtop/ramtop.c A src/soc/amd/common/block/uma/Kconfig A src/soc/amd/common/block/uma/Makefile.inc A src/soc/amd/common/block/uma/uma.c 8 files changed, 136 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/37402/1
diff --git a/src/soc/amd/common/block/include/amdblocks/biosram_layout.h b/src/soc/amd/common/block/include/amdblocks/biosram_layout.h new file mode 100644 index 0000000..2ca4f74 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/biosram_layout.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_BIOSRAM_H__ +#define __AMDBLOCKS_BIOSRAM_H__ + +/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ +#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ +#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ + +#endif diff --git a/src/soc/amd/common/block/include/amdblocks/uma.h b/src/soc/amd/common/block/include/amdblocks/uma.h new file mode 100644 index 0000000..939713d --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/uma.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_UMA_H__ +#define __AMDBLOCKS_UMA_H__ + +/* Saves the UMA size returned by AGESA */ +void save_uma_size(uint32_t size); +/* Saves the UMA base address returned by AGESA */ +void save_uma_base(uint64_t base); +/* Returns the saved UMA size */ +uint32_t get_uma_size(void); +/* Returns the saved UMA base */ +uint64_t get_uma_base(void); + +#endif diff --git a/src/soc/amd/common/block/ramtop/Kconfig b/src/soc/amd/common/block/ramtop/Kconfig new file mode 100644 index 0000000..36bf074 --- /dev/null +++ b/src/soc/amd/common/block/ramtop/Kconfig @@ -0,0 +1,7 @@ +config SOC_AMD_COMMON_BLOCK_RAMTOP + bool + default n + depends on SOC_AMD_COMMON_BLOCK_ACPIMMIO + help + Select this option to enable common cbmem top save and restore + functions usign BIOSRAM. diff --git a/src/soc/amd/common/block/ramtop/Makefile.inc b/src/soc/amd/common/block/ramtop/Makefile.inc new file mode 100644 index 0000000..bb2d290 --- /dev/null +++ b/src/soc/amd/common/block/ramtop/Makefile.inc @@ -0,0 +1,3 @@ +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RAMTOP) += ramtop.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_RAMTOP) += ramtop.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RAMTOP) += ramtop.c diff --git a/src/soc/amd/common/block/ramtop/ramtop.c b/src/soc/amd/common/block/ramtop/ramtop.c new file mode 100644 index 0000000..ae93537 --- /dev/null +++ b/src/soc/amd/common/block/ramtop/ramtop.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cbmem.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/biosram_layout.h> + +void backup_top_of_low_cacheable(uintptr_t ramtop) +{ + biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); +} + +uintptr_t restore_top_of_low_cacheable(void) +{ + return biosram_read32(BIOSRAM_CBMEM_TOP); +} diff --git a/src/soc/amd/common/block/uma/Kconfig b/src/soc/amd/common/block/uma/Kconfig new file mode 100644 index 0000000..8b0e18a --- /dev/null +++ b/src/soc/amd/common/block/uma/Kconfig @@ -0,0 +1,7 @@ +config SOC_AMD_COMMON_BLOCK_UMA + bool + default n + depends on SOC_AMD_COMMON_BLOCK_ACPIMMIO + help + Select this option to enable common UMA parameters save and + restore functions using BIOSRAM. diff --git a/src/soc/amd/common/block/uma/Makefile.inc b/src/soc/amd/common/block/uma/Makefile.inc new file mode 100644 index 0000000..b3bb8c6 --- /dev/null +++ b/src/soc/amd/common/block/uma/Makefile.inc @@ -0,0 +1,3 @@ +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UMA) += uma.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_UMA) += uma.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UMA) += uma.c diff --git a/src/soc/amd/common/block/uma/uma.c b/src/soc/amd/common/block/uma/uma.c new file mode 100644 index 0000000..00b4642 --- /dev/null +++ b/src/soc/amd/common/block/uma/uma.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/biosram_layout.h> +#include <amdblocks/uma.h> + +void save_uma_size(uint32_t size) +{ + biosram_write32(BIOSRAM_UMA_SIZE, size); +} + +void save_uma_base(uint64_t base) +{ + biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); + biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); +} + +uint32_t get_uma_size(void) +{ + return biosram_read32(BIOSRAM_UMA_SIZE); +} + +uint64_t get_uma_base(void) +{ + uint64_t base; + base = biosram_read32(BIOSRAM_UMA_BASE); + base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); + return base; +}
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: soc/amd/common/blocks: introduce two new BIOSRAM based common blocks ......................................................................
Patch Set 1:
Should be possible right after CB:37382 or even before it. I would have expected code move from amd/stoneyridge here but did not check closer yet (-1 from jenkins).
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: soc/amd/common/blocks: introduce two new BIOSRAM based common blocks ......................................................................
Patch Set 1:
(2 comments)
You can combine new ramtop.c and uma.c and make it acpimmio/biosram.c.
https://review.coreboot.org/c/coreboot/+/37402/1/src/soc/amd/common/block/in... File src/soc/amd/common/block/include/amdblocks/biosram_layout.h:
https://review.coreboot.org/c/coreboot/+/37402/1/src/soc/amd/common/block/in... PS1, Line 21: Bring prototypes from uma.h here and remove that file. You can remove _layout from filename too.
https://review.coreboot.org/c/coreboot/+/37402/1/src/soc/amd/common/block/ra... File src/soc/amd/common/block/ramtop/Kconfig:
https://review.coreboot.org/c/coreboot/+/37402/1/src/soc/amd/common/block/ra... PS1, Line 1: config SOC_AMD_COMMON_BLOCK_RAMTOP I am pretty sure we can do with just SOC_AMD_COMMON_BLOCK_BIOSRAM.
We expand/split this if we ever find a reason to do so.
Hello Kyösti Mälkki, Marshall Dawson, Richard Spiegel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37402
to look at the new patch set (#3).
Change subject: soc/amd/common/blocks/acpimmio: extend the block with BIOSRAM storage ......................................................................
soc/amd/common/blocks/acpimmio: extend the block with BIOSRAM storage
All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size.
Create unified BIOSRAM layout and add implementation for cbmem top and UMA storing. Also replace the existing implementation of cbmem top and UMA with the BIOSRAM access.
TEST=boot PC Engines apu1 and apu2
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da --- M src/northbridge/amd/pi/Makefile.inc D src/northbridge/amd/pi/ramtop.c M src/soc/amd/common/block/acpimmio/Makefile.inc A src/soc/amd/common/block/acpimmio/biosram.c A src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c M src/southbridge/amd/agesa/hudson/ramtop.c M src/southbridge/amd/cimx/sb800/ramtop.c 16 files changed, 93 insertions(+), 220 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/37402/3
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: soc/amd/common/blocks/acpimmio: extend the block with BIOSRAM storage ......................................................................
Patch Set 3:
(2 comments)
Patch Set 1:
(2 comments)
You can combine new ramtop.c and uma.c and make it acpimmio/biosram.c.
Done. Merged it into ACPIMMIO and squashed with CB:37402.
https://review.coreboot.org/c/coreboot/+/37402/1/src/soc/amd/common/block/in... File src/soc/amd/common/block/include/amdblocks/biosram_layout.h:
https://review.coreboot.org/c/coreboot/+/37402/1/src/soc/amd/common/block/in... PS1, Line 21:
Bring prototypes from uma.h here and remove that file. You can remove _layout from filename too.
Done
https://review.coreboot.org/c/coreboot/+/37402/1/src/soc/amd/common/block/ra... File src/soc/amd/common/block/ramtop/Kconfig:
https://review.coreboot.org/c/coreboot/+/37402/1/src/soc/amd/common/block/ra... PS1, Line 1: config SOC_AMD_COMMON_BLOCK_RAMTOP
I am pretty sure we can do with just SOC_AMD_COMMON_BLOCK_BIOSRAM. […]
I just merged it with ACPIMMIO.
Hello Kyösti Mälkki, Marshall Dawson, Richard Spiegel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37402
to look at the new patch set (#4).
Change subject: soc/amd/common/blocks/acpimmio: extend the block with BIOSRAM storage ......................................................................
soc/amd/common/blocks/acpimmio: extend the block with BIOSRAM storage
All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size.
Create unified BIOSRAM layout and add implementation for cbmem top, UMA storing and AP bootblock entry. Also replace the existing implementation of cbmem top, UMA and AP entry with the BIOSRAM access.
TEST=boot PC Engines apu1 and apu2
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da --- M src/northbridge/amd/pi/Makefile.inc D src/northbridge/amd/pi/ramtop.c M src/soc/amd/common/block/acpimmio/Makefile.inc A src/soc/amd/common/block/acpimmio/biosram.c A src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/memmap.c D src/soc/amd/stoneyridge/nb_util.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c M src/soc/amd/stoneyridge/southbridge.c M src/southbridge/amd/agesa/hudson/ramtop.c M src/southbridge/amd/cimx/sb800/ramtop.c 21 files changed, 111 insertions(+), 273 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/37402/4
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: soc/amd/common/blocks/acpimmio: extend the block with BIOSRAM storage ......................................................................
Patch Set 4:
Looks mostly good, did not check for details. set/get_ap_entry can go into same acpimmio/biosram.c and prototypes in biosram.h. Followup, remove respective code from amd/stoneyridge and followups do not need nb_util.c
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: soc/amd/common/blocks/acpimmio: extend the block with BIOSRAM storage ......................................................................
Patch Set 4:
Patch Set 4:
Looks mostly good, did not check for details. set/get_ap_entry can go into same acpimmio/biosram.c and prototypes in biosram.h. Followup, remove respective code from amd/stoneyridge and followups do not need nb_util.c
Done locally, will push in a sec
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: soc/amd/common/blocks/acpimmio: extend the block with BIOSRAM storage ......................................................................
Patch Set 5:
Please keep ap_entry as separate change. It does not originate from BIOSRAM.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: soc/amd/common/blocks/acpimmio: extend the block with BIOSRAM storage ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37402/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37402/5//COMMIT_MSG@7 PS5, Line 7: soc/amd/common/blocks/acpimmio: extend the block with BIOSRAM storage amdblocks/acpimmio: Unify BIOSRAM usage
https://review.coreboot.org/c/coreboot/+/37402/5//COMMIT_MSG@15 PS5, Line 15: of cbmem top, UMA and AP entry with the BIOSRAM access. Except for AP entry we are not really creating anything new, just moving the already existing stoney/picasso code to common/.
Hello Kyösti Mälkki, Marshall Dawson, Richard Spiegel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37402
to look at the new patch set (#6).
Change subject: amdblocks/acpimmio: Unify BIOSRAM usage ......................................................................
amdblocks/acpimmio: Unify BIOSRAM usage
All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size.
Unify BIOSRAM layout and add implementation for cbmem top and UMA storing. Also replace the existing implementation of cbmem top and UMA with the BIOSRAM access.
TEST=boot PC Engines apu1 and apu2
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da --- M src/northbridge/amd/pi/Makefile.inc D src/northbridge/amd/pi/ramtop.c M src/soc/amd/common/block/acpimmio/Makefile.inc A src/soc/amd/common/block/acpimmio/biosram.c A src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c M src/southbridge/amd/agesa/hudson/ramtop.c M src/southbridge/amd/cimx/sb800/ramtop.c 16 files changed, 94 insertions(+), 220 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/37402/6
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: amdblocks/acpimmio: Unify BIOSRAM usage ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37402/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37402/5//COMMIT_MSG@7 PS5, Line 7: soc/amd/common/blocks/acpimmio: extend the block with BIOSRAM storage
amdblocks/acpimmio: Unify BIOSRAM usage
Done
https://review.coreboot.org/c/coreboot/+/37402/5//COMMIT_MSG@15 PS5, Line 15: of cbmem top, UMA and AP entry with the BIOSRAM access.
Except for AP entry we are not really creating anything new, just moving the already existing stoney […]
Done
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: amdblocks/acpimmio: Unify BIOSRAM usage ......................................................................
Patch Set 7:
I don't see the changes done to hudson and sb800 as working, as I don't see a change in their makefile.inc to use the common code. IIRC, you're only getting away with it because Kyosti disabled the build of several old AMD platforms, hudson and sb800 included...
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: amdblocks/acpimmio: Unify BIOSRAM usage ......................................................................
Patch Set 7: Code-Review+2
Patch Set 7:
I don't see the changes done to hudson and sb800 as working, as I don't see a change in their makefile.inc to use the common code. IIRC, you're only getting away with it because Kyosti disabled the build of several old AMD platforms, hudson and sb800 included...
The change to use common code is already in with previous "select SOC_AMD_COMMON_ACPIMMIO" for these platforms. All AGESA boards still build.
Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: amdblocks/acpimmio: Unify BIOSRAM usage ......................................................................
Patch Set 8: Code-Review+2
Patch Set 7: Code-Review+2
Patch Set 7:
I don't see the changes done to hudson and sb800 as working, as I don't see a change in their makefile.inc to use the common code. IIRC, you're only getting away with it because Kyosti disabled the build of several old AMD platforms, hudson and sb800 included...
The change to use common code is already in with previous "select SOC_AMD_COMMON_ACPIMMIO" for these platforms. All AGESA boards still build.
Well, in this case, I agree... approved.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: amdblocks/acpimmio: Unify BIOSRAM usage ......................................................................
Patch Set 8: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/37402/8/src/soc/amd/common/block/ac... File src/soc/amd/common/block/acpimmio/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37402/8/src/soc/amd/common/block/ac... PS8, Line 8: bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c nit: isn't there an `all-` target that could be used instead?
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37402 )
Change subject: amdblocks/acpimmio: Unify BIOSRAM usage ......................................................................
amdblocks/acpimmio: Unify BIOSRAM usage
All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size.
Unify BIOSRAM layout and add implementation for cbmem top and UMA storing. Also replace the existing implementation of cbmem top and UMA with the BIOSRAM access.
TEST=boot PC Engines apu1 and apu2
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402 Reviewed-by: Richard Spiegel richard.spiegel@silverbackltd.com Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/amd/pi/Makefile.inc D src/northbridge/amd/pi/ramtop.c M src/soc/amd/common/block/acpimmio/Makefile.inc A src/soc/amd/common/block/acpimmio/biosram.c A src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c M src/southbridge/amd/agesa/hudson/ramtop.c M src/southbridge/amd/cimx/sb800/ramtop.c 16 files changed, 94 insertions(+), 220 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Richard Spiegel: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index ffafc60..61917c9 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -19,7 +19,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01
-romstage-y += ramtop.c -postcar-y += ramtop.c -ramstage-y += ramtop.c endif diff --git a/src/northbridge/amd/pi/ramtop.c b/src/northbridge/amd/pi/ramtop.c deleted file mode 100644 index 823a15c..0000000 --- a/src/northbridge/amd/pi/ramtop.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <device/pci_ops.h> -#include <cbmem.h> - -#define CBMEM_TOP_SCRATCHPAD 0x78 - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - uint16_t top_cache = ramtop >> 16; - pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache); -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - uint16_t top_cache; - top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD); - return (top_cache << 16); -} diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc index 9517b10..69253b9 100644 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -4,3 +4,10 @@ postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c + +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c new file mode 100644 index 0000000..f0a1257 --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/biosram.h> + +void backup_top_of_low_cacheable(uintptr_t ramtop) +{ + biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); +} + +uintptr_t restore_top_of_low_cacheable(void) +{ + return biosram_read32(BIOSRAM_CBMEM_TOP); +} + +void save_uma_size(uint32_t size) +{ + biosram_write32(BIOSRAM_UMA_SIZE, size); +} + +void save_uma_base(uint64_t base) +{ + biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); + biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); +} + +uint32_t get_uma_size(void) +{ + return biosram_read32(BIOSRAM_UMA_SIZE); +} + +uint64_t get_uma_base(void) +{ + uint64_t base; + base = biosram_read32(BIOSRAM_UMA_BASE); + base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); + return base; +} diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h new file mode 100644 index 0000000..e2c1eb3 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_BIOSRAM_H__ +#define __AMDBLOCKS_BIOSRAM_H__ + +#include <stdint.h> + +/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ +#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ +#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ + +/* Saves the UMA size returned by AGESA */ +void save_uma_size(uint32_t size); +/* Saves the UMA base address returned by AGESA */ +void save_uma_base(uint64_t base); +/* Returns the saved UMA size */ +uint32_t get_uma_size(void); +/* Returns the saved UMA base */ +uint64_t get_uma_base(void); + +#endif diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index c5464df..4584216 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -18,11 +18,11 @@ #include <cbmem.h> #include <console/console.h> #include <timestamp.h> +#include <amdblocks/biosram.h> #include <amdblocks/s3_resume.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/BiosCallOuts.h> #include <soc/pci_devs.h> -#include <soc/southbridge.h> #include <soc/northbridge.h> #include <soc/cpu.h>
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 0fb187d..cbf95b9 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -335,38 +335,6 @@ void fch_pre_init(void); void fch_early_init(void); void set_uart_config(int idx); -/** - * @brief Save the UMA bize - * - * @param size = in bytes - * - * @return none - */ -void save_uma_size(uint32_t size); -/** - * @brief Save the UMA base address - * - * @param base = 64bit base address - * - * @return none - */ -void save_uma_base(uint64_t base); -/** - * @brief Get the saved UMA size - * - * @param none - * - * @return size in bytes - */ -uint32_t get_uma_size(void); -/** - * @brief Get the saved UMA base - * - * @param none - * - * @return 64bit base address - */ -uint64_t get_uma_base(void);
/* Initialize all the i2c buses that are marked with early init. */ void i2c_soc_early_init(void); diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 82d6fb6..ae5a331 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -28,16 +28,6 @@ #include <soc/iomap.h> #include <amdblocks/acpimmio.h>
-void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - return biosram_read32(BIOSRAM_CBMEM_TOP); -} - #if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0 #define BERT_REGION_MAX_SIZE 0x100000 diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 08807f3..4a1493c 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/biosram.h> #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> @@ -29,7 +30,6 @@ #include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/northbridge.h> -#include <soc/southbridge.h> #include <soc/pci_devs.h> #include <soc/iomap.h> #include <stdint.h> diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 041d262..0dff4bc 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -501,27 +501,3 @@ * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index dd514ab..0555afb 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -350,38 +350,7 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); void bootblock_fch_early_init(void); void bootblock_fch_init(void); -/** - * @brief Save the UMA bize returned by AGESA - * - * @param size = in bytes - * - * @return none - */ -void save_uma_size(uint32_t size); -/** - * @brief Save the UMA base address returned by AGESA - * - * @param base = 64bit base address - * - * @return none - */ -void save_uma_base(uint64_t base); -/** - * @brief Get the saved UMA size - * - * @param none - * - * @return size in bytes - */ -uint32_t get_uma_size(void); -/** - * @brief Get the saved UMA base - * - * @param none - * - * @return 64bit base address - */ -uint64_t get_uma_base(void); + /* * Call the mainboard to get the USB Over Current Map. The mainboard * returns the map and 0 on Success or -1 on error or no map. There is diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 82d6fb6..ae5a331 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -28,16 +28,6 @@ #include <soc/iomap.h> #include <amdblocks/acpimmio.h>
-void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - return biosram_read32(BIOSRAM_CBMEM_TOP); -} - #if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0 #define BERT_REGION_MAX_SIZE 0x100000 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 044a1b0..c98d0a9 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/biosram.h> #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> @@ -32,7 +33,6 @@ #include <agesa_headers.h> #include <soc/cpu.h> #include <soc/northbridge.h> -#include <soc/southbridge.h> #include <soc/pci_devs.h> #include <soc/iomap.h> #include <stdint.h> diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 85c7eaf..1b2afec 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -648,27 +648,3 @@ * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c index 22b291d..2af95df 100644 --- a/src/southbridge/amd/agesa/hudson/ramtop.c +++ b/src/southbridge/amd/agesa/hudson/ramtop.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <arch/io.h> #include <arch/acpi.h> -#include <cbmem.h> #include "hudson.h"
int acpi_get_sleep_type(void) @@ -25,27 +24,3 @@ tmp = ((tmp & (7 << 10)) >> 10); return (int)tmp; } - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - u32 dword = ramtop; - int nvram_pos = 0xf8, i; /* temp */ - for (i = 0; i < 4; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xf8, xi; - for (xi = 0; xi < 4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return xdata; -} diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c index b9fc00d..98d12c7 100644 --- a/src/southbridge/amd/cimx/sb800/ramtop.c +++ b/src/southbridge/amd/cimx/sb800/ramtop.c @@ -25,27 +25,3 @@ tmp = ((tmp & (7 << 10)) >> 10); return (int)tmp; } - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - u32 dword = ramtop; - int nvram_pos = 0xf8, i; /* temp */ - for (i = 0; i < 4; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - u32 xdata = 0; - int xnvram_pos = 0xf8, xi; - for (xi = 0; xi < 4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi * 8); - xnvram_pos++; - } - return xdata; -}
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