Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28857
Change subject: src: Move IA32_PACKAGE_THERM_INTERRUPT to x86/msr.h ......................................................................
src: Move IA32_PACKAGE_THERM_INTERRUPT to x86/msr.h
Change-Id: I738c337c7eed9be6c1ae6dcc03c60af399f83196 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/fsp_model_206ax/model_206ax.h M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/haswell.h M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/include/cpu/x86/msr.h M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/cannonlake/include/soc/msr.h M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/skylake/include/soc/msr.h 10 files changed, 1 insertion(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28857/1
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h index 46c7a65..470c6ba 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h @@ -26,7 +26,6 @@ #define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 #define IA32_MC0_STATUS 0x401
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 5d9b8d3..c23a87e 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -27,7 +27,6 @@ #define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 #define IA32_MC0_STATUS 0x401
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 97c1abe..b718616 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -41,7 +41,6 @@ #define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 #define IA32_MC0_STATUS 0x401
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index aeb113a..c4ca738 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -28,7 +28,6 @@ #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_FERR_CAPABILITY 0x1f1 #define FERR_ENABLE (1 << 0) -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 2f28799..0ad2329 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -26,7 +26,6 @@ #define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 #define IA32_MC0_STATUS 0x401
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 9148349..77b6b4b 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -28,6 +28,7 @@ #define IA32_MISC_ENABLE 0x1a0 /* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */ #define BURST_MODE_DISABLE (1 << 6) +#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_IA32_PAT 0x277 #define IA32_BIOS_UPDT_TRIG 0x79 #define IA32_BIOS_SIGN_ID 0x8b diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 40a9340..0bdf29e 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -33,7 +33,6 @@ #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define EMRRphysBase_MSR 0x1f4 #define EMRRphysMask_MSR 0x1f5 #define IA32_PLATFORM_DCA_CAP 0x1f8 diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h index f8a342c..c85def4 100644 --- a/src/soc/intel/cannonlake/include/soc/msr.h +++ b/src/soc/intel/cannonlake/include/soc/msr.h @@ -20,7 +20,6 @@ #include <intelblocks/msr.h>
#define MSR_PIC_MSG_CONTROL 0x2e -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define IA32_PLATFORM_DCA_CAP 0x1f9 #define MSR_VR_MISC_CONFIG2 0x636
diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 58d4cfe..73c5675 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -35,7 +35,6 @@ #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define EMRR_PHYS_BASE_MSR 0x1f4 #define EMRR_PHYS_MASK_MSR 0x1f5 #define IA32_PLATFORM_DCA_CAP 0x1f8 diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index a371e47..a1bb0fc 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -24,7 +24,6 @@ #define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_DELAY_VALUE 0x13 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
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Elyes HAOUAS (Code Review)