Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63931 )
Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge ......................................................................
Patch Set 4: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63931/comment/fa2a9635_f81ddb64 PS2, Line 9: On this mainboard there are legacy PCI device, which are connected to
I have reworded the statement.
Ack
Commit Message:
https://review.coreboot.org/c/coreboot/+/63931/comment/740074bf_743d8417 PS4, Line 10: PCI PCIe
https://review.coreboot.org/c/coreboot/+/63931/comment/fd8c8db5_b617e5ae PS4, Line 10: ports are in use clock outputs of this bridge are used.
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Werner Zeh (Code Review)