Change in coreboot[master]: mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

mediatek/mt8192: add spmfw loader

To support mt8192 power saving during suspend to RAM, this patch loads
spmfw to support SPM suspend. SPM needs its own firmware to do these
power saving in the right timing under correct conditions.
After linux PM suspends, SPM is able to turn off more power saving for
the SoC such as DRAM self-refresh mode and turning off 26M crystal.

BUG=b:159079649
TEST=Asurada boots up to shell

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/common/mtcmos.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,551 insertions(+), 32 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/1

diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c
index 76a71c7..7b3ef22 100644
--- a/src/mainboard/google/asurada/mainboard.c
+++ b/src/mainboard/google/asurada/mainboard.c
@@ -6,6 +6,7 @@
 #include <device/mmio.h>
 #include <lib.h>
 #include <soc/gpio_common.h>
+#include <soc/spm.h>
 #include <soc/usb.h>

#include "gpio.h"
@@ -77,6 +78,9 @@
    setup_usb_host();

register_reset_to_bl31();
+
+	if (spm_init())
+		printk(BIOS_ERR, "spm init fail, system suspend may stuck\n");
 }

static void mainboard_enable(struct device *dev)
diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c
index cfd148c..0bba19e 100644
--- a/src/soc/mediatek/common/mtcmos.c
+++ b/src/soc/mediatek/common/mtcmos.c
@@ -23,7 +23,7 @@

static void mtcmos_power_on(const struct power_domain_data *pd)
 {
-	write32(&mtk_spm->poweron_config_set,
+	write32(&mtk_spm->poweron_config_en,
    	(SPM_PROJECT_CODE << 16) | (1U << 0));

setbits32(pd->pwr_con, PWR_ON);
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 891d38a..d417ae2 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -33,6 +33,7 @@
 ramstage-y += ../common/gpio.c gpio.c
 ramstage-y += emi.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+ramstage-y += spm.c
 ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += soc.c
@@ -42,6 +43,11 @@

MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192

+cbfs-files-y += spm_firmware.bin
+spm_firmware.bin-file := $(MT8192_BLOB_DIR)/spm_firmware.bin
+spm_firmware.bin-type := raw
+spm_firmware.bin-compression := $(CBFS_COMPRESS_FLAG)
+
 DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram
 $(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf
 $(DRAM_CBFS)-type := stage
diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h
index 73ef798..53b86e5 100644
--- a/src/soc/mediatek/mt8192/include/soc/spm.h
+++ b/src/soc/mediatek/mt8192/include/soc/spm.h
@@ -4,10 +4,309 @@
 #define SOC_MEDIATEK_MT8192_SPM_H

#include <soc/addressmap.h>
+#include <stdint.h>
 #include <types.h>

/* SPM READ/WRITE CFG */
-#define SPM_PROJECT_CODE	0xb16
+#define SPM_PROJECT_CODE                    (0xb16)
+#define SPM_REGWR_CFG_KEY                   (SPM_PROJECT_CODE << 16)
+
+/* POWERON_CONFIG_EN (0x10006000+0x000) */
+#define BCLK_CG_EN_LSB                      (1U << 0)       /* 1b */
+
+/* SPM_CLK_CON (0x10006000+0x00C) */
+#define REG_SYSCLK1_SRC_MD2_SRCCLKENA       (1U << 28)      /* 1b */
+
+/* PCM_CON0 (0x10006000+0x018) */
+#define PCM_CK_EN_LSB                       (1U << 2)       /* 1b */
+#define PCM_SW_RESET_LSB                    (1U << 15)      /* 1b */
+
+/* PCM_CON1 (0x10006000+0x01C) */
+#define RG_IM_SLAVE_LSB                     (1U << 0)       /* 1b */
+#define RG_AHBMIF_APBEN_LSB                 (1U << 3)       /* 1b */
+#define RG_PCM_TIMER_EN_LSB                 (1U << 5)       /* 1b */
+#define SPM_EVENT_COUNTER_CLR_LSB           (1U << 6)       /* 1b */
+#define RG_PCM_WDT_WAKE_LSB                 (1U << 9)       /* 1b */
+#define REG_SPM_SRAM_ISOINT_B_LSB           (1U << 11)      /* 1b */
+#define REG_EVENT_LOCK_EN_LSB               (1U << 12)      /* 1b */
+#define REG_MD32_APB_INTERNAL_EN_LSB        (1U << 14)      /* 1b */
+
+/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */
+#define SPM_WAKEUP_EVENT_MASK_BIT0          (1U << 0)       /* 1b */
+#define SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B   (1U << 24)      /* 1b */
+
+/* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */
+#define REG_ALL_DDR_EN_DBC_EN_LSB           (1U << 0)       /* 1b */
+
+/* SPM_DVFS_MISC (0x10006000+0x4AC) */
+#define SPM_DVFS_FORCE_ENABLE_LSB           (1U << 2)       /* 1b */
+#define SPM_DVFSRC_ENABLE_LSB               (1U << 4)       /* 1b */
+
+/* SPM_SW_FLAG_0 (0x10006000+0x600) */
+#define SPM_FLAG_DISABLE_VCORE_DVS          (1U << 3)       /* 1b */
+#define SPM_FLAG_DISABLE_VCORE_DFS          (1U << 4)       /* 1b */
+#define SPM_FLAG_RUN_COMMON_SCENARIO        (1U << 10)      /* 1b */
+
+/* SYS_TIMER_CON (0x10006000+0x98C) */
+#define SYS_TIMER_START_EN_LSB              (1U << 0)       /* 1b */
+
+/* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */
+#define MD32PCM_CFGREG_SW_RSTN_RESET        (1U << 0)       /* 1b */
+
+/**************************************
+ * Config and Parameter
+ **************************************/
+#define POWER_ON_VAL1_DEF                   (0x80015860)
+#define SPM_WAKEUP_EVENT_MASK_DEF           (0xefffffff)
+#define SPM_ACK_CHK_3_SEL_HW_S1             (0x00350098)
+#define SPM_ACK_CHK_3_HW_S1_CNT             (0x1)
+#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG      (0x800)
+#define SPM_ACK_CHK_3_CON_EN                (0x110)
+#define SPM_ACK_CHK_3_CON_CLR_ALL           (0x2)
+#define SPM_BUS_PROTECT_MASK_B_DEF          (0xffffffff)
+#define SPM_BUS_PROTECT2_MASK_B_DEF         (0xffffffff)
+#define MD32PCM_DMA0_CON_VAL                (0x0003820e)
+#define MD32PCM_DMA0_START_VAL              (0x00008000)
+#define MD32PCM_CFGREG_SW_RSTN_RUN          (0x1)
+#define SPM_DVFS_LEVEL_DEF                  (0x00000001)
+#define SPM_DVS_DFS_LEVEL_DEF               (0x00010001)
+#define SPM_RESOURCE_ACK_CON0_DEF           (0x00000000)
+#define SPM_RESOURCE_ACK_CON1_DEF           (0x00000000)
+#define SPM_RESOURCE_ACK_CON2_DEF           (0xcccc4e4e)
+#define SPM_RESOURCE_ACK_CON3_DEF           (0x00000000)
+#define ARMPLL_CLK_SEL_DEF                  (0x3ff)
+#define DDR_EN_DBC_CON0_DEF                 (0x154)
+#define SPM_SYSCLK_SETTLE                   (0x60fe)
+#define SPM_INIT_DONE_US                    (20)
+#define PCM_WDT_TIMEOUT                     (30 * 32768)
+#define PCM_TIMER_MAX                       (0xffffffff - PCM_WDT_TIMEOUT)
+
+/**************************************
+ * Define and Declare
+ **************************************/
+/* SPM_IRQ_MASK */
+#define ISRM_TWAM                           (1U << 2)
+#define ISRM_PCM_RETURN                     (1U << 3)
+#define ISRM_RET_IRQ_AUX                    (0x3fe00)
+#define ISRM_ALL_EXC_TWAM                   (ISRM_RET_IRQ_AUX)
+#define ISRM_ALL                            (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
+
+/* SPM_IRQ_STA */
+#define ISRS_TWAM                           (1U << 2)
+#define ISRS_PCM_RETURN                     (1U << 3)
+#define ISRC_TWAM                           ISRS_TWAM
+#define ISRC_ALL_EXC_TWAM                   ISRS_PCM_RETURN
+#define ISRC_ALL                            (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
+
+/* PCM_PWR_IO_EN */
+#define PCM_PWRIO_EN_R0                     (1U << 0)
+#define PCM_PWRIO_EN_R7                     (1U << 7)
+#define PCM_RF_SYNC_R0                      (1U << 16)
+#define PCM_RF_SYNC_R6                      (1U << 22)
+#define PCM_RF_SYNC_R7                      (1U << 23)
+
+/* SPM_SWINT */
+#define PCM_SW_INT_ALL                      (0x3ff)
+
+struct pwr_ctrl {
+	u32 pcm_flags;
+	u32 pcm_flags_cust;
+	u32 pcm_flags_cust_set;
+	u32 pcm_flags_cust_clr;
+	u32 pcm_flags1;
+	u32 pcm_flags1_cust;
+	u32 pcm_flags1_cust_set;
+	u32 pcm_flags1_cust_clr;
+	u32 timer_val;
+	u32 timer_val_cust;
+	u32 timer_val_ramp_en;
+	u32 timer_val_ramp_en_sec;
+	u32 wake_src;
+	u32 wake_src_cust;
+	u32 wakelock_timer_val;
+	u8 wdt_disable;
+
+	/* Auto-gen Start */
+
+	/* SPM_CLK_CON */
+	u8 reg_srcclken0_ctl;
+	u8 reg_srcclken1_ctl;
+	u8 reg_spm_lock_infra_dcm;
+	u8 reg_srcclken_mask;
+	u8 reg_md1_c32rm_en;
+	u8 reg_md2_c32rm_en;
+	u8 reg_clksq0_sel_ctrl;
+	u8 reg_clksq1_sel_ctrl;
+	u8 reg_srcclken0_en;
+	u8 reg_srcclken1_en;
+	u32 reg_sysclk0_src_mask_b;
+	u32 reg_sysclk1_src_mask_b;
+
+	/* SPM_AP_STANDBY_CON */
+	u8 reg_wfi_op;
+	u8 reg_wfi_type;
+	u8 reg_mp0_cputop_idle_mask;
+	u8 reg_mp1_cputop_idle_mask;
+	u8 reg_mcusys_idle_mask;
+	u8 reg_md_apsrc_1_sel;
+	u8 reg_md_apsrc_0_sel;
+	u8 reg_conn_apsrc_sel;
+
+	/* SPM_SRC6_MASK */
+	u8 reg_dpmaif_srcclkena_mask_b;
+	u8 reg_dpmaif_infra_req_mask_b;
+	u8 reg_dpmaif_apsrc_req_mask_b;
+	u8 reg_dpmaif_vrf18_req_mask_b;
+	u8 reg_dpmaif_ddr_en_mask_b;
+
+	/* SPM_SRC_REQ */
+	u8 reg_spm_apsrc_req;
+	u8 reg_spm_f26m_req;
+	u8 reg_spm_infra_req;
+	u8 reg_spm_vrf18_req;
+	u8 reg_spm_ddr_en_req;
+	u8 reg_spm_dvfs_req;
+	u8 reg_spm_sw_mailbox_req;
+	u8 reg_spm_sspm_mailbox_req;
+	u8 reg_spm_adsp_mailbox_req;
+	u8 reg_spm_scp_mailbox_req;
+
+	/* SPM_SRC_MASK */
+	u8 reg_md_srcclkena_0_mask_b;
+	u8 reg_md_srcclkena2infra_req_0_mask_b;
+	u8 reg_md_apsrc2infra_req_0_mask_b;
+	u8 reg_md_apsrc_req_0_mask_b;
+	u8 reg_md_vrf18_req_0_mask_b;
+	u8 reg_md_ddr_en_0_mask_b;
+	u8 reg_md_srcclkena_1_mask_b;
+	u8 reg_md_srcclkena2infra_req_1_mask_b;
+	u8 reg_md_apsrc2infra_req_1_mask_b;
+	u8 reg_md_apsrc_req_1_mask_b;
+	u8 reg_md_vrf18_req_1_mask_b;
+	u8 reg_md_ddr_en_1_mask_b;
+	u8 reg_conn_srcclkena_mask_b;
+	u8 reg_conn_srcclkenb_mask_b;
+	u8 reg_conn_infra_req_mask_b;
+	u8 reg_conn_apsrc_req_mask_b;
+	u8 reg_conn_vrf18_req_mask_b;
+	u8 reg_conn_ddr_en_mask_b;
+	u8 reg_conn_vfe28_mask_b;
+	u8 reg_srcclkeni0_srcclkena_mask_b;
+	u8 reg_srcclkeni0_infra_req_mask_b;
+	u8 reg_srcclkeni1_srcclkena_mask_b;
+	u8 reg_srcclkeni1_infra_req_mask_b;
+	u8 reg_srcclkeni2_srcclkena_mask_b;
+	u8 reg_srcclkeni2_infra_req_mask_b;
+	u8 reg_infrasys_apsrc_req_mask_b;
+	u8 reg_infrasys_ddr_en_mask_b;
+	u8 reg_md32_srcclkena_mask_b;
+	u8 reg_md32_infra_req_mask_b;
+	u8 reg_md32_apsrc_req_mask_b;
+	u8 reg_md32_vrf18_req_mask_b;
+	u8 reg_md32_ddr_en_mask_b;
+
+	/* SPM_SRC2_MASK */
+	u8 reg_scp_srcclkena_mask_b;
+	u8 reg_scp_infra_req_mask_b;
+	u8 reg_scp_apsrc_req_mask_b;
+	u8 reg_scp_vrf18_req_mask_b;
+	u8 reg_scp_ddr_en_mask_b;
+	u8 reg_audio_dsp_srcclkena_mask_b;
+	u8 reg_audio_dsp_infra_req_mask_b;
+	u8 reg_audio_dsp_apsrc_req_mask_b;
+	u8 reg_audio_dsp_vrf18_req_mask_b;
+	u8 reg_audio_dsp_ddr_en_mask_b;
+	u8 reg_ufs_srcclkena_mask_b;
+	u8 reg_ufs_infra_req_mask_b;
+	u8 reg_ufs_apsrc_req_mask_b;
+	u8 reg_ufs_vrf18_req_mask_b;
+	u8 reg_ufs_ddr_en_mask_b;
+	u8 reg_disp0_apsrc_req_mask_b;
+	u8 reg_disp0_ddr_en_mask_b;
+	u8 reg_disp1_apsrc_req_mask_b;
+	u8 reg_disp1_ddr_en_mask_b;
+	u8 reg_gce_infra_req_mask_b;
+	u8 reg_gce_apsrc_req_mask_b;
+	u8 reg_gce_vrf18_req_mask_b;
+	u8 reg_gce_ddr_en_mask_b;
+	u8 reg_apu_srcclkena_mask_b;
+	u8 reg_apu_infra_req_mask_b;
+	u8 reg_apu_apsrc_req_mask_b;
+	u8 reg_apu_vrf18_req_mask_b;
+	u8 reg_apu_ddr_en_mask_b;
+	u8 reg_cg_check_srcclkena_mask_b;
+	u8 reg_cg_check_apsrc_req_mask_b;
+	u8 reg_cg_check_vrf18_req_mask_b;
+	u8 reg_cg_check_ddr_en_mask_b;
+
+	/* SPM_SRC3_MASK */
+	u8 reg_dvfsrc_event_trigger_mask_b;
+	u8 reg_sw2spm_int0_mask_b;
+	u8 reg_sw2spm_int1_mask_b;
+	u8 reg_sw2spm_int2_mask_b;
+	u8 reg_sw2spm_int3_mask_b;
+	u8 reg_sc_adsp2spm_wakeup_mask_b;
+	u8 reg_sc_sspm2spm_wakeup_mask_b;
+	u8 reg_sc_scp2spm_wakeup_mask_b;
+	u8 reg_csyspwrreq_mask;
+	u8 reg_spm_srcclkena_reserved_mask_b;
+	u8 reg_spm_infra_req_reserved_mask_b;
+	u8 reg_spm_apsrc_req_reserved_mask_b;
+	u8 reg_spm_vrf18_req_reserved_mask_b;
+	u8 reg_spm_ddr_en_reserved_mask_b;
+	u8 reg_mcupm_srcclkena_mask_b;
+	u8 reg_mcupm_infra_req_mask_b;
+	u8 reg_mcupm_apsrc_req_mask_b;
+	u8 reg_mcupm_vrf18_req_mask_b;
+	u8 reg_mcupm_ddr_en_mask_b;
+	u8 reg_msdc0_srcclkena_mask_b;
+	u8 reg_msdc0_infra_req_mask_b;
+	u8 reg_msdc0_apsrc_req_mask_b;
+	u8 reg_msdc0_vrf18_req_mask_b;
+	u8 reg_msdc0_ddr_en_mask_b;
+	u8 reg_msdc1_srcclkena_mask_b;
+	u8 reg_msdc1_infra_req_mask_b;
+	u8 reg_msdc1_apsrc_req_mask_b;
+	u8 reg_msdc1_vrf18_req_mask_b;
+	u8 reg_msdc1_ddr_en_mask_b;
+
+	/* SPM_SRC4_MASK */
+	u32 ccif_event_mask_b;
+	u8 reg_bak_psri_srcclkena_mask_b;
+	u8 reg_bak_psri_infra_req_mask_b;
+	u8 reg_bak_psri_apsrc_req_mask_b;
+	u8 reg_bak_psri_vrf18_req_mask_b;
+	u8 reg_bak_psri_ddr_en_mask_b;
+	u8 reg_dramc0_md32_infra_req_mask_b;
+	u8 reg_dramc0_md32_vrf18_req_mask_b;
+	u8 reg_dramc1_md32_infra_req_mask_b;
+	u8 reg_dramc1_md32_vrf18_req_mask_b;
+	u8 reg_conn_srcclkenb2pwrap_mask_b;
+	u8 reg_dramc0_md32_wakeup_mask;
+	u8 reg_dramc1_md32_wakeup_mask;
+
+	/* SPM_SRC5_MASK */
+	u32 reg_mcusys_merge_apsrc_req_mask_b;
+	u32 reg_mcusys_merge_ddr_en_mask_b;
+	u8 reg_msdc2_srcclkena_mask_b;
+	u8 reg_msdc2_infra_req_mask_b;
+	u8 reg_msdc2_apsrc_req_mask_b;
+	u8 reg_msdc2_vrf18_req_mask_b;
+	u8 reg_msdc2_ddr_en_mask_b;
+	u8 reg_pcie_srcclkena_mask_b;
+	u8 reg_pcie_infra_req_mask_b;
+	u8 reg_pcie_apsrc_req_mask_b;
+	u8 reg_pcie_vrf18_req_mask_b;
+	u8 reg_pcie_ddr_en_mask_b;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	u32 reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	u32 reg_ext_wakeup_event_mask;
+
+	/* Auto-gen End */
+};

enum {
    DISP_PWR_STA_MASK	= 0x1 << 20,
@@ -19,7 +318,7 @@
 };

struct mtk_spm_regs {
-	u32 poweron_config_set;
+	u32 poweron_config_en;
    u32 spm_power_on_val0;
    u32 spm_power_on_val1;
    u32 spm_clk_con;
@@ -34,14 +333,14 @@
    u32 pcm_timer_val;
    u32 pcm_wdt_val;
    u32 spm_src6_mask;
-	u32 reserved1[1];
-	u32 spm_sw_rst_con;	/* 0x0040 */
+	u32 reserved0;
+	u32 spm_sw_rst_con;
    u32 spm_sw_rst_con_set;
    u32 spm_sw_rst_con_clr;
    u32 vs1_psr_mask_b;
    u32 vs2_psr_mask_b;
-	u32 reserved2[12];
-	u32 md32_clk_con;	/* 0x0084 */
+	u32 reserved1[12];
+	u32 md32_clk_con;
    u32 spm_sram_rsv_con;
    u32 spm_swint;
    u32 spm_swint_set;
@@ -77,27 +376,27 @@
    u32 pcm_reg6_data;
    u32 pcm_reg7_data;
    u32 pcm_reg13_data;
-	u32 src_req_sta_0;
-	u32 src_req_sta_1;
-	u32 src_req_sta_2;
+	u32 src_req_sta0;
+	u32 src_req_sta1;
+	u32 src_req_sta2;
    u32 pcm_timer_out;
    u32 pcm_wdt_out;
    u32 spm_irq_sta;
-	u32 src_req_sta_4;
+	u32 src_req_sta4;
    u32 md32pcm_wakeup_sta;
    u32 md32pcm_event_sta;
    u32 spm_wakeup_sta;
    u32 spm_wakeup_ext_sta;
    u32 spm_wakeup_misc;
    u32 mm_dvfs_halt;
-	u32 reserved3[2];
-	u32 bus_protect_rdy;	/* 0x0150 */
+	u32 reserved2[2];
+	u32 bus_protect_rdy;
    u32 bus_protect1_rdy;
    u32 bus_protect2_rdy;
    u32 bus_protect3_rdy;
    u32 subsys_idle_sta;
    u32 pcm_sta;
-	u32 src_req_sta_3;
+	u32 src_req_sta3;
    u32 pwr_status;
    u32 pwr_status_2nd;
    u32 cpu_pwr_status;
@@ -109,15 +408,15 @@
    u32 spm_ddren_event_count_sta;
    u32 md32pcm_sta;
    u32 md32pcm_pc;
-	u32 reserved4[3];
-	u32 dvfsrc_event_sta;	/* 0x01a4 */
+	u32 reserved3[3];
+	u32 dvfsrc_event_sta;
    u32 bus_protect4_rdy;
    u32 bus_protect5_rdy;
    u32 bus_protect6_rdy;
    u32 bus_protect7_rdy;
    u32 bus_protect8_rdy;
-	u32 reserved5[5];
-	u32 spm_twam_last_sta0;	/* 0x01d0 */
+	u32 reserved4[5];
+	u32 spm_twam_last_sta0;
    u32 spm_twam_last_sta1;
    u32 spm_twam_last_sta2;
    u32 spm_twam_last_sta3;
@@ -139,8 +438,8 @@
    u32 spm_cpu5_pwr_con;
    u32 spm_cpu6_pwr_con;
    u32 spm_cpu7_pwr_con;
-	u32 reserved6[1];
-	u32 armpll_clk_con;	/* 0x022c */
+	u32 reserved5;
+	u32 armpll_clk_con;
    u32 mcusys_idle_sta;
    u32 gic_wakeup_sta;
    u32 cpu_spare_con;
@@ -150,8 +449,8 @@
    u32 ext_int_wakeup_req;
    u32 ext_int_wakeup_req_set;
    u32 ext_int_wakeup_req_clr;
-	u32 reserved7[3];
-	u32 mp0_cpu0_irq_mask;	/* 0x0260 */
+	u32 reserved6[3];
+	u32 mp0_cpu0_irq_mask;
    u32 mp0_cpu1_irq_mask;
    u32 mp0_cpu2_irq_mask;
    u32 mp0_cpu3_irq_mask;
@@ -169,8 +468,8 @@
    u32 mp0_cpu7_wfi_en;
    u32 root_cputop_addr;
    u32 root_core_addr;
-	u32 reserved8[10];
-	u32 spm2sw_mailbox_0;	/* 0x02d0 */
+	u32 reserved7[10];
+	u32 spm2sw_mailbox_0;
    u32 spm2sw_mailbox_1;
    u32 spm2sw_mailbox_2;
    u32 spm2sw_mailbox_3;
@@ -227,22 +526,147 @@
    u32 debugtop_sram_con;
    u32 dp_tx_pwr_con;
    u32 dpmaif_sram_con;
-	u32 dpy_shu2_sram_con;
+	u32 dpy_shu2_con;
    u32 dramc_mcu2_sram_con;
    u32 dramc_mcu_sram_con;
    u32 mcupm_pwr_con;
    u32 dpy2_pwr_con;
    u32 peri_pwr_con;
+	u32 reserved8[13];
+	u32 spm_mem_ck_sel;
+	u32 spm_bus_protect_mask_b;
+	u32 spm_bus_protect1_mask_b;
+	u32 spm_bus_protect2_mask_b;
+	u32 spm_bus_protect3_mask_b;
+	u32 spm_bus_protect4_mask_b;
+	u32 spm_emi_bw_mode;
+	u32 ap2md_peer_wakeup;
+	u32 ulposc_con;
+	u32 spm2mm_con;
+	u32 spm_bus_protect5_mask_b;
+	u32 spm2mcupm_con;
+	u32 ap_mdsrc_req;
+	u32 spm2emi_enter_ulpm;
+	u32 spm2md_dvfs_con;
+	u32 md2spm_dvfs_con;
+	u32 spm_bus_protect6_mask_b;
+	u32 spm_bus_protect7_mask_b;
+	u32 spm_bus_protect8_mask_b;
+	u32 spm_pll_con;
+	u32 cpu_dvfs_req;
+	u32 spm_dram_mcu_sw_con0;
+	u32 spm_dram_mcu_sw_con1;
+	u32 spm_dram_mcu_sw_con2;
+	u32 spm_dram_mcu_sw_con3;
+	u32 spm_dram_mcu_sw_con4;
+	u32 spm_dram_mcu_sta_0;
+	u32 spm_dram_mcu_sta_1;
+	u32 spm_dram_mcu_sta_2;
+	u32 spm_dram_mcu_sw_sel_0;
+	u32 relay_dvfs_level;
+	u32 reserved9;
+	u32 dramc_dpy_clk_sw_con_0;
+	u32 dramc_dpy_clk_sw_con_1;
+	u32 dramc_dpy_clk_sw_con_2;
+	u32 dramc_dpy_clk_sw_con_3;
+	u32 dramc_dpy_clk_sw_sel_0;
+	u32 dramc_dpy_clk_sw_sel_1;
+	u32 dramc_dpy_clk_sw_sel_2;
+	u32 dramc_dpy_clk_sw_sel_3;
+	u32 dramc_dpy_clk_spm_con;
+	u32 spm_dvfs_level;
+	u32 spm_cirq_con;
+	u32 spm_dvfs_misc;
+	u32 spm_vs1_vs2_rc_con;
+	u32 rg_module_sw_cg_0_mask_req_0;
+	u32 rg_module_sw_cg_0_mask_req_1;
+	u32 rg_module_sw_cg_0_mask_req_2;
+	u32 rg_module_sw_cg_1_mask_req_0;
+	u32 rg_module_sw_cg_1_mask_req_1;
+	u32 rg_module_sw_cg_1_mask_req_2;
+	u32 rg_module_sw_cg_2_mask_req_0;
+	u32 rg_module_sw_cg_2_mask_req_1;
+	u32 rg_module_sw_cg_2_mask_req_2;
+	u32 rg_module_sw_cg_3_mask_req_0;
+	u32 rg_module_sw_cg_3_mask_req_1;
+	u32 rg_module_sw_cg_3_mask_req_2;
+	u32 pwr_status_mask_req_0;
+	u32 pwr_status_mask_req_1;
+	u32 pwr_status_mask_req_2;
+	u32 spm_cg_check_con;
+	u32 spm_src_rdy_sta;
+	u32 spm_dvs_dfs_level;
+	u32 spm_force_dvfs;
+	u32 reserved10[64];
+	u32 spm_sw_flag_0;
+	u32 spm_sw_debug_0;
+	u32 spm_sw_flag_1;
+	u32 reserved11[8];
+	u32 spm_sw_rsv_7;
+	u32 spm_sw_rsv_8;
+	u32 reserved12[203];
+	u32 spm_ack_chk_con_3;
+	u32 spm_ack_chk_pc_3;
+	u32 spm_ack_chk_sel_3;
+	u32 spm_ack_chk_timer_3;
+	u32 reserved13[7];
+	u32 sys_timer_con;
+	u32 reserved14[28];
+	u32 md32pcm_cfgreg_sw_rstn;
+	u32 reserved15[127];
+	u32 md32pcm_dma0_src;
+	u32 md32pcm_dma0_dst;
+	u32 md32pcm_dma0_wppt;
+	u32 md32pcm_dma0_wpto;
+	u32 md32pcm_dma0_count;
+	u32 md32pcm_dma0_con;
+	u32 md32pcm_dma0_start;
+	u32 reserved16[2];
+	u32 md32pcm_dma0_rlct;
 };
-
-check_member(mtk_spm_regs, md32_clk_con, 0x0084);
-check_member(mtk_spm_regs, bus_protect_rdy, 0x0150);
-check_member(mtk_spm_regs, dvfsrc_event_sta, 0x01a4);
-check_member(mtk_spm_regs, spm_twam_last_sta0, 0x01d0);
-check_member(mtk_spm_regs, mp0_cpu0_irq_mask, 0x0260);
+check_member(mtk_spm_regs, poweron_config_en, 0x0);
+check_member(mtk_spm_regs, vs2_psr_mask_b, 0x50);
+check_member(mtk_spm_regs, md32_clk_con, 0x84);
+check_member(mtk_spm_regs, mm_dvfs_halt, 0x144);
+check_member(mtk_spm_regs, bus_protect_rdy, 0x150);
+check_member(mtk_spm_regs, md32pcm_pc, 0x194);
+check_member(mtk_spm_regs, dvfsrc_event_sta, 0x1a4);
+check_member(mtk_spm_regs, bus_protect8_rdy, 0x1b8);
+check_member(mtk_spm_regs, spm_twam_last_sta0, 0x1d0);
+check_member(mtk_spm_regs, ext_int_wakeup_req_clr, 0x250);
+check_member(mtk_spm_regs, mp0_cpu0_irq_mask, 0x260);
+check_member(mtk_spm_regs, root_core_addr, 0x2a4);
 check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x02d0);
-check_member(mtk_spm_regs, peri_pwr_con, 0x03c8);
+check_member(mtk_spm_regs, peri_pwr_con, 0x3c8);
+check_member(mtk_spm_regs, spm_mem_ck_sel, 0x400);
+check_member(mtk_spm_regs, spm_force_dvfs, 0x4fc);
+check_member(mtk_spm_regs, spm_sw_flag_0, 0x600);
+check_member(mtk_spm_regs, spm_sw_flag_1, 0x608);
+check_member(mtk_spm_regs, spm_sw_rsv_7, 0x62c);
+check_member(mtk_spm_regs, spm_sw_rsv_8, 0x630);
+check_member(mtk_spm_regs, spm_ack_chk_con_3, 0x960);
+check_member(mtk_spm_regs, spm_ack_chk_timer_3, 0x96c);
+check_member(mtk_spm_regs, sys_timer_con, 0x98c);
+check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xa00);
+check_member(mtk_spm_regs, md32pcm_dma0_src, 0xc00);
+check_member(mtk_spm_regs, md32pcm_dma0_dst, 0xc04);
+check_member(mtk_spm_regs, md32pcm_dma0_wppt, 0xc08);
+check_member(mtk_spm_regs, md32pcm_dma0_wpto, 0xc0c);
+check_member(mtk_spm_regs, md32pcm_dma0_count, 0xc10);
+check_member(mtk_spm_regs, md32pcm_dma0_con, 0xc14);
+check_member(mtk_spm_regs, md32pcm_dma0_start, 0xc18);
+check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xc24);

static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;

+struct spm_desc {
+	const char *version;
+	u32 pmem_words;
+	u32 total_words;
+	u32 pmem_start;
+	u32 dmem_start;
+};
+
+int spm_init(void);
+
 #endif  /* SOC_MEDIATEK_MT8192_SPM_H */
diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c
new file mode 100644
index 0000000..578a637
--- /dev/null
+++ b/src/soc/mediatek/mt8192/spm.c
@@ -0,0 +1,1085 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <soc/spm.h>
+#include <timer.h>
+
+static const u32 spm_firmware_binary[] = {
+	0x3200001e, 0x6a00001e, 0x6e00001e, 0x6800001e, 0x6200001e, 0x6000001e,
+	0x5e00001e, 0x5c00001e, 0x6000001e, 0x5800001e, 0x5600001e, 0x5400001e,
+	0x5200001e, 0x5000001e, 0x4e00001e, 0x4c00001e, 0xd402001e, 0xee01001e,
+	0x3a03001e, 0x0002001e, 0x3609001e, 0xfa01001e, 0xf601001e, 0xf201001e,
+	0xee01001e, 0x000f0f98, 0x300d0e00, 0x000fee00, 0x380d0100, 0x000f1160,
+	0x380d0200, 0x001c22d8, 0x01041218, 0x1c0423e1, 0x000c3262, 0x801c3303,
+	0xf0064014, 0x00090104, 0x831d2201, 0x801c40f8, 0xd0066010, 0x00090101,
+	0x831d3301, 0x150460f8, 0x000d0140, 0x18041101, 0x03931020, 0x001f0493,
+	0x1393b912, 0x0400001f, 0x0000001e, 0xc0051198, 0x3fa02000, 0x00008005,
+	0x0000a005, 0x0000a005, 0x0000a005, 0xe1a70292, 0x0300f2a7, 0x82ac018c,
+	0x84ad03ad, 0x86ae05ae, 0x02ace2a5, 0x018b0300, 0x000802a8, 0x02ac2201,
+	0xf2a5e1a5, 0xa005ee97, 0x00000000, 0x01200000, 0x31060013, 0x0621500f,
+	0x3f200040, 0x010d0900, 0x07a8a80f, 0xa80d6188, 0x250f77a8, 0x250d0625,
+	0x87b46625, 0x2fa086b4, 0x06ac87b4, 0x7f0cbc13, 0x0621500f, 0x3f200040,
+	0x07a8a80f, 0x010d0900, 0x8a0d6188, 0x8a0f778a, 0x250f088a, 0xa80d0625,
+	0x87b488a8, 0x57520200, 0x2fa086b4, 0x07ac88b4, 0x01000200, 0x31060013,
+	0x0621500f, 0x3f200040, 0x0710200f, 0x01100900, 0x720d6188, 0xf3017744,
+	0xf70696c5, 0xf89f7190, 0x6150f006, 0x06ff080f, 0x66ffbb0d, 0x8150f006,
+	0xc7b3f501, 0x81ecfc06, 0xf80ff001, 0xf10606b5, 0x2fa07150, 0x8110f006,
+	0x008008ac, 0x01000200, 0x13060011, 0x0721500f, 0x3f200040, 0x01100900,
+	0x0810200f, 0x1e0d7188, 0xfe0f8804, 0x3c0d07ff, 0xf0017758, 0xf706a200,
+	0x000f8190, 0xf006063c, 0x380d7150, 0xf00f663c, 0xf006073c, 0x180d2150,
+	0xfc06773c, 0xf00121ec, 0x06b51800, 0x7150f106, 0xf0062fa0, 0x08ac8110,
+	0x81890300, 0xc8890300, 0x0f0f07a8, 0xff0d01ff, 0xf00f16ff, 0x718a0100,
+	0x0700300f, 0x774c680d, 0x61a871ac, 0x71280b45, 0x618b2fa0, 0x008061b6,
+	0x01800000, 0x08002fa0, 0x00070600, 0x00806165, 0x01800000, 0x800cc0f3,
+	0x11bb1100, 0x01800000, 0x06000800, 0x0700300f, 0x778c640d, 0x61640007,
+	0x000c61a8, 0x9f1c11f0, 0x3fa030fa, 0x00803fa0, 0xa0c921a8, 0x02202fa0,
+	0x21ac1144, 0x80c921a8, 0x31a821ac, 0x31b408c9, 0x2fa031a8, 0x31b680c9,
+	0x31681e04, 0x0600300f, 0x668c6908, 0x2fa008c9, 0x50ac51ac, 0x08c921a8,
+	0x21a821b4, 0x21b480c9, 0x20c921a8, 0x21a821b4, 0x21b490c9, 0x2fa021a8,
+	0x21b698c9, 0x0f0d21a8, 0x21b41100, 0x08c921a8, 0x21a821b4, 0x21b420c9,
+	0x80c921a8, 0x21a821b4, 0x21b490c9, 0x2fa021a8, 0x21b698c9, 0x81860300,
+	0x000c01a8, 0x31bc1104, 0x3f200040, 0x0100300f, 0x1120640d, 0x9dc906a8,
+	0x02202fa0, 0x06b66633, 0x28c921a8, 0x21a821b4, 0x21b4b0c9, 0x2fa021a8,
+	0x21b6c8c9, 0x0100300f, 0x11346008, 0x0600f000, 0x07160b0f, 0x7708000d,
+	0x6110f006, 0x8734fb4f, 0x71ecff06, 0x6110f006, 0x87b42fa0, 0x008007ac,
+	0x0100300f, 0x11346008, 0x0600f000, 0x07160b0f, 0x7708000d, 0x6110f006,
+	0x8734fb4f, 0x71ecff06, 0x6110f006, 0x87b42fa0, 0x008007ac, 0x0100300f,
+	0x1150680d, 0x0700100f, 0x87c908a8, 0x00000fc9, 0xf1060210, 0x040081d0,
+	0x87b50801, 0x86890300, 0x21d4f206, 0x56a808ac, 0x6600100c, 0x0700300f,
+	0x06a846bc, 0x06ac1dc9, 0x01004000, 0x0600300f, 0x66b0600d, 0x12650007,
+	0x78be58a8, 0x00008005, 0x831c58a8, 0x00a000fb, 0x12640007, 0x0100300f,
+	0x1134660d, 0x890406a8, 0x831c66fc, 0x2fa0c0fa, 0x71b06008, 0x008000ac,
+	0xe1a70292, 0xf6270b4c, 0x01140000, 0x40f328f2, 0xe1a5f6a5, 0xa005ee97,
+	0x00800000, 0x0000a005, 0x0000a005, 0x0000a005, 0x0000a005, 0x0000a005,
+	0x0100300f, 0x0300100f, 0x18086a08, 0x37003f0d, 0x101ac014, 0x06001000,
+	0x00a08049, 0x71ac3044, 0x28584006, 0x4006e2b4, 0xe2b4285c, 0x06100000,
+	0x31803f08, 0x87b435f3, 0x87b475f3, 0x87b4b5f3, 0x87b4f5f3, 0x76440007,
+	0x000787b4, 0x87b47645, 0x76460007, 0x000787b4, 0x87b47647, 0x76480007,
+	0x000787b4, 0x87b47649, 0x764a0007, 0x2fa087b4, 0x66510007, 0x008006ac,
+	0x0000a4b9, 0x31a80114, 0x31c01120, 0x31a831ac, 0x11bd8904, 0x119c8904,
+	0x312c0040, 0x890431a8, 0x831c11fe, 0x31a820fa, 0x11bc8904, 0x89042fa0,
+	0x31ac119d, 0x90f268f3, 0x831c68f3, 0x3fa0c0fe, 0x01100000, 0x0697010f,
+	0x01600007, 0x07ff010f, 0x68721b4c, 0x00072fa0, 0x28f27166, 0x300f0192,
+	0x6b0d0800, 0x424c8800, 0xfd0fffa7, 0x74a801ff, 0x11ebff0d, 0x0499418a,
+	0x1810f206, 0x01540900, 0x0400f5b4, 0xf4b40500, 0x0416000f, 0x1200f1b4,
+	0xf5b401a8, 0xf1b4f4b4, 0x03ff1f0f, 0x31f8ff0d, 0xff06f0b4, 0xf80608d8,
+	0x4b061800, 0x0300180c, 0x03004388, 0x03008287, 0xf94f078a, 0x030021ac,
+	0x10ac0688, 0x01140000, 0x0b4c60ac, 0x0007502c, 0x00070163, 0x28f20162,
+	0x18004606, 0x11998904, 0x02800000, 0xaeff1f17, 0x18007606, 0x01800000,
+	0x9172fb4f, 0x170b0000, 0x61650007, 0x68004b06, 0x4b0668f2, 0x00076804,
+	0x4b066164, 0x00076820, 0x7b066171, 0xffa57828, 0xfe972fa0, 0x00800080,
+	0xd6a70b92, 0x76401504, 0xc4a7b3a7, 0x63401504, 0x54401504, 0x300f66a7,
+	0x6d0d0600, 0x91a76600, 0x74a7f8a7, 0xe7a7a2a7, 0x83a75fa7, 0x9ec957a8,
+	0x0100020f, 0x7600fd06, 0x0ec957a8, 0x1114000d, 0x7600f106, 0x718b57a8,
+	0x08adde0f, 0x87adde0d, 0x16fcf906, 0x4f0657ac, 0x40801630, 0x0400300f,
+	0x300fa1bc, 0x680d0100, 0x06a81150, 0x66938904, 0x06360040, 0xfafe1f1f,
+	0x0600500f, 0x41006c08, 0x6600600d, 0x0700100f, 0x78003a0d, 0x000086b4,
+	0x08b506b9, 0x08140000, 0x380087b7, 0x06b5e720, 0x06000800, 0x87b488b4,
+	0x66a506ac, 0x83a574a5, 0x67201804, 0x45201804, 0x36201804, 0x91a55fa5,
+	0xe7a5a2a5, 0xd6a5f8a5, 0xb3a5c4a5, 0xa0055e97, 0x00800000, 0xf8a70592,
+	0x0800300f, 0x6a08d6a7, 0xe04b8620, 0xe7a7b1a7, 0x56a950ac, 0x06a806ac,
+	0x6608c6b8, 0x01a88734, 0x864c680d, 0x420661ac, 0x0ba11718, 0x119b8904,
+	0x81346608, 0x8650680d, 0x420600ac, 0x40c9111c, 0x87306d08, 0x880c0000,
+	0x68ac51ac, 0xd6a5b1a5, 0xf8a5e7a5, 0xa005be97, 0x00800000, 0x03000192,
+	0xffa78889, 0x200c71a8, 0x91ba1100, 0x0100300f, 0x11346008, 0x0600f000,
+	0x062c0040, 0x02800000, 0x01200000, 0x06000100, 0x0540000f, 0x12650007,
+	0x62640007, 0x52640007, 0x00208249, 0xb6fe1f17, 0xc3300000, 0x0700300f,
+	0x7700660d, 0x52650007, 0x50c961a8, 0x61aa61b6, 0xffa571ac, 0xfe972fa0,
+	0x00800080, 0x38f00049, 0xffa704f0, 0x00c971a8, 0xe3050000, 0x71a871b4,
+	0xff0188c9, 0x1f17f700, 0x71b495fe, 0x178a71a8, 0xffa577b6, 0xfe972fa0,
+	0x00800080, 0x37f00049, 0x61a8ffa7, 0xd1b94080, 0xc014ffa5, 0x00800812,
+	0x00a0204c, 0x880466a8, 0x11866601, 0x049366ac, 0x78fe1f17, 0xc3090000,
+	0x000d61a8, 0x61b41106, 0x80c961a8, 0xffa561b6, 0xfe972fa0, 0x00200040,
+	0xfe972fa0, 0x00800080, 0x37f00049, 0x61a8ffa7, 0x80144080, 0xffa5204e,
+	0x0810c014, 0x41980080, 0x880466a8, 0x11866601, 0x000066ac, 0xc0f30180,
+	0x1130000c, 0x200c8414, 0xc3090000, 0x00a0a14d, 0x48fe1f17, 0x00208249,
+	0x000d61a8, 0x61b41106, 0x80c961a8, 0xffa561b6, 0xfe972fa0, 0x00200040,
+	0xfe972fa0, 0x00800080, 0xffa70192, 0x000c21a8, 0x84141120, 0xffa5200e,
+	0xfe972fa0, 0x00200040, 0x21a89b49, 0x000048c9, 0x61b40680, 0x000cc5f3,
+	0x00001130, 0x841cc309, 0x439b2006, 0x1afe1f17, 0x00208249, 0x30c961a8,
+	0x61a861b4, 0x61b6a8c9, 0x2fa0ffa5, 0x0080fe97, 0x006d8014, 0x07140000,
+	0x0700300f, 0x7780690d, 0x112061a8, 0x61ac61c0, 0x890461a8, 0x890411bd,
+	0x61ac119c, 0x17844d06, 0x1102000c, 0xfd0881bb, 0x300f7184, 0x680d0800,
+	0x00a08850, 0x890466a8, 0x76bc66fe, 0x890476a8, 0xc349629c, 0x52b60020,
+	0x000c06a8, 0x831c6602, 0x00a0c0e6, 0x890461a8, 0x004011bc, 0x89042f20,
+	0x61b6119d, 0xaef246f3, 0x418a21a8, 0x51fe7f1d, 0x46f32fa0, 0x07620007,
+	0x4670ac49, 0x0200300f, 0x2204670d, 0x07003000, 0x718a11a8, 0x20fc8315,
+	0x0100300f, 0x12006708, 0x124c2498, 0x670d13ac, 0x1f161304, 0x100fabff,
+	0x00800700, 0x300f0192, 0x600d0100, 0x93bb11dc, 0x8949ffa7, 0x049908f0,
+	0x21a8824c, 0x080f18c9, 0x21ac0700, 0x96ff1f17, 0x46920000, 0x13744706,
+	0x770668c9, 0xffa51374, 0xfe972fa0, 0x00200040, 0x05f08949, 0x0870824c,
+	0xcc6421a8, 0x040f0020, 0x21ac0700, 0x7eff1f17, 0x46920000, 0x13744706,
+	0x770670c9, 0xffa51374, 0xfe972fa0, 0x00800080, 0x300f0192, 0x600d0b00,
+	0xf000b934, 0x0b0f0100, 0x000d0616, 0xffa76a08, 0x1910f006, 0xa904f006,
+	0xa9ecff06, 0x19084106, 0x51b84080, 0x2fa0ffa5, 0x0080fe97, 0x0d800000,
+	0x300f019a, 0x6a0d0600, 0x00076624, 0x56a81d61, 0x000066b9, 0x00070710,
+	0x300f1d62, 0x680d0100, 0x06a81150, 0x04003dc9, 0xf1068800, 0xf20661dc,
+	0x08ac71d4, 0x2fa0ffa5, 0x0080fe97, 0x8c890300, 0x1c004006, 0x1140000c,
+	0x20c88114, 0xb7a86408, 0x1c004006, 0x1100200c, 0x1f1741be, 0x139859fc,
+	0x1c004006, 0x1100200c, 0x4006a1be, 0x080c1c00, 0x51be1100, 0x74ff1f17,
+	0x00a08149, 0x1c004006, 0x1100200c, 0x4006a1bc, 0x400c1c00, 0x81151100,
+	0x67082006, 0x00a0bb08, 0x1c004006, 0x1100200c, 0x030061b9, 0x01a88186,
+	0x1100040c, 0x059301bb, 0x44100000, 0x3aff1f17, 0x00a0294c, 0x0100300f,
+	0x1150680d, 0x890406a8, 0x06b66691, 0x0200300f, 0x224c680d, 0x11a81398,
+	0x00208464, 0x04100000, 0xe8fb1f17, 0x12e0f106, 0x1c004006, 0x11bc8904,
+	0xf50f0000, 0x96fb1f17, 0x1c007006, 0x3204f306, 0x890483f3, 0x83f211b6,
+	0x400615ac, 0x200c1c00, 0x80151100, 0x0000206a, 0x20000880, 0x02000100,
+	0x00070200, 0x04931864, 0xccfc1f17, 0x00a0a14c, 0x0700300f, 0x7720610d,
+	0x28640007, 0x61287b4e, 0x87870300, 0x61ac1298, 0x1d430007, 0x20c9618a,
+	0x0710000f, 0x0000c7f2, 0x00070104, 0x04002d61, 0x00070280, 0x00077d61,
+	0x00071865, 0x00072865, 0x0b451d43, 0x000d0020, 0xc7f26130, 0xf006f19f,
+	0xf0061910, 0x7006a904, 0xffa5a900, 0xfe972fa0, 0x00200040, 0xf1050000,
+	0x44100000, 0x1b007006, 0xc4fe1f17, 0x05f0514c, 0x00000593, 0x1f174410,
+	0xb398bdfe, 0x00000593, 0x1f174410, 0x9398b7fe, 0xf1040000, 0x70060593,
+	0x00001b00, 0x1f174410, 0xa398adfe, 0x00000593, 0x1f174410, 0xb398a7fe,
+	0x00000593, 0x1f174410, 0x7398a1fe, 0x00000593, 0x1f174410, 0x93989bfe,
+	0x31080000, 0x1b48f106, 0x1b004006, 0x11958904, 0x48ff1f16, 0x1b007006,
+	0x04f0084c, 0x0020444c, 0x17a8f306, 0x52fc1f17, 0xe3040000, 0x8d610007,
+	0x78c961a8, 0x12ff1f16, 0x008061ac, 0x300f0192, 0x60080d00, 0xf000d134,
+	0x0b0f0600, 0x000d0716, 0xffa77908, 0x6110f006, 0x8a890300, 0x09ac89b4,
+	0x1a004006, 0x1100200c, 0x20848015, 0x41880300, 0x1f170493, 0x03a82bfc,
+	0x0100300f, 0x113c610d, 0x890406a8, 0x831466f3, 0x0000c0fa, 0x00000780,
+	0x000f0604, 0x00070110, 0x86f26764, 0x16fc1f17, 0x43100000, 0x02000200,
+	0x00071198, 0x784e2765, 0xeef386f2, 0x20c9618a, 0x0600300f, 0x6620610d,
+	0xc506c6f2, 0x03001618, 0x0300028a, 0x11ac8887, 0x78a811a8, 0x03008189,
+	0x20000888, 0x71ac0200, 0x71a853a8, 0x51ac3188, 0x27650007, 0x1a004006,
+	0x1100200c, 0x030061b9, 0x01a88186, 0x1100040c, 0x059301bb, 0x44100000,
+	0x14fe1f17, 0x00a0214c, 0x0100300f, 0x1150680d, 0x890406a8, 0x06b66692,
+	0x1a004006, 0x1100200c, 0x4006a1bc, 0x400c1a00, 0x80151100, 0x670820c6,
+	0x00a0dc08, 0x00208249, 0xc4fb1f17, 0x43100000, 0x1a004006, 0x1100200c,
+	0x4006a1be, 0x080c1a00, 0x51be1100, 0x04fe1f17, 0x00a0094c, 0x1a004006,
+	0x1100200c, 0x1f1741be, 0x0393d3fa, 0x1a004006, 0x1140000c, 0x000021bb,
+	0x434c0180, 0x64080470, 0xa8f2d7a8, 0x07a8f306, 0x9cfb1f17, 0xe3040000,
+	0x890461a8, 0x61ac1190, 0x01800000, 0x0370034d, 0x0400300f, 0x444c680d,
+	0xa872f94f, 0x806431a8, 0x1f170020, 0x31ac7ffa, 0x1a004006, 0x119c8904,
+	0x30fa1f17, 0x1af0ff06, 0x14e0c106, 0x580c218c, 0x000d1100, 0xf8061106,
+	0x7e061400, 0x7e062408, 0x7e069418, 0xffa5941c, 0xfe972fa0, 0x00200040,
+	0xfb050000, 0x70060593, 0x0000bc00, 0x1f174410, 0x839895fd, 0xf1040000,
+	0x70060593, 0x00001c00, 0x1f174410, 0x83988bfd, 0xbc007006, 0x05708249,
+	0x50fb1f17, 0x43100000, 0x44100000, 0x7efd1f17, 0x00a0694c, 0x00000593,
+	0x1f174410, 0xc39877fd, 0xf1040000, 0x70060593, 0x00001c00, 0x1f174410,
+	0x63986dfd, 0x00000593, 0x1f174410, 0xd39867fd, 0x3b080000, 0x00000593,
+	0x1f174410, 0xc3985ffd, 0xbc48f106, 0x1c004006, 0x11968904, 0x62ff1f16,
+	0x1c007006, 0x37f00049, 0x43708249, 0x61a8ffa7, 0x1f1710c9, 0x61b417fb,
+	0x8c6461a8, 0x1f170020, 0x61b411fb, 0xa0c961a8, 0x61a861b4, 0x61b488c9,
+	0x00c961a8, 0x61a861b4, 0x1f17c0c9, 0x61b403fb, 0xe46461a8, 0x1f170020,
+	0x61b4fdfa, 0xe86461a8, 0x1f170020, 0x61b4f7fa, 0xd8c961a8, 0xffa561b6,
+	0xf0fa1f16, 0x0080fe97, 0x37f00049, 0x43708249, 0x61a8ffa7, 0x1f1718c9,
+	0x61b4e5fa, 0x886461a8, 0x1f170020, 0x61b4dffa, 0x88c961a8, 0x61a861b4,
+	0x61b4a0c9, 0x00c961a8, 0xffa561b6, 0xfe972fa0, 0x00800080, 0x80150192,
+	0xffa76822, 0x0100300f, 0x11a4640d, 0x801501a8, 0x500f2112, 0x08000600,
+	0x61880103, 0x06ac1698, 0x61108014, 0x0100800f, 0x3104001c, 0x86f91f1f,
+	0x0700800f, 0x00153193, 0x00003705, 0x11980680, 0x0700010f, 0x16700007,
+	0x76640007, 0x164c0007, 0x11f08904, 0x20f8831c, 0x76650007, 0x680c8015,
+	0x2fa0ffa5, 0x0080fe97, 0x640c8015, 0x2fa0ffa5, 0x0080fe97, 0x1f16ffa5,
+	0xfe9759f9, 0x300f0792, 0x600d0b00, 0xf000ba34, 0x0b0f0100, 0x000d0616,
+	0x9fa76c08, 0x1a10f006, 0xca04f006, 0xcaecff06, 0xda704106, 0x8a704406,
+	0xd804001c, 0xad3e0040, 0xb1a46408, 0x08ac00ac, 0x2fa09fa5, 0x00809e97,
+	0x3cf91f1f, 0x0500300f, 0x55f8640d, 0xf94c5793, 0xcf064128, 0x21206780,
+	0x00816620, 0xf6a766ac, 0x67844d06, 0x66542120, 0x0011a013, 0x02006289,
+	0x00190600, 0x00a06d0b, 0x06000200, 0x001bd993, 0xa01b8609, 0x00a0a00f,
+	0x06200000, 0x69e20904, 0x000de011, 0xe0190693, 0x16982007, 0x692cf94c,
+	0x77844d06, 0x77542120, 0x27e70104, 0x02800300, 0x27370020, 0x222067a8,
+	0xe2a77210, 0x72202220, 0x77781c04, 0x0114d2a7, 0xc7a7061d, 0x89040013,
+	0x02931298, 0xf6250a4c, 0x6704001c, 0x00208249, 0xb6a71698, 0x001ce6a5,
+	0xb0a71603, 0x48ff1f17, 0x03100000, 0x41448115, 0x81890300, 0xc08141a8,
+	0x41a841b4, 0x0320c6a5, 0x41b41106, 0x81890300, 0x01a8a5a7, 0x1108000c,
+	0x801461be, 0x0a4c80ce, 0x00a0d3a5, 0x81890300, 0x000c01a8, 0x91bb1110,
+	0x71bfb1a5, 0x74f81f17, 0x00a0c949, 0x2cf81f1f, 0xb2246408, 0x00a0f84c,
+	0xe1a511ac, 0x18ff1f17, 0x13701e04, 0x3af81f17, 0x10acc949, 0x04f81f1f,
+	0xd4f81f17, 0x00a0414c, 0x06a8a1a5, 0x0100f001, 0xa6a53045, 0x51a851b4,
+	0xb845e7a5, 0x51b600a0, 0xb8a46408, 0xfcfe1f17, 0x03200000, 0x1f1770ac,
+	0x79ac8df8, 0xd9140014, 0xb62c6a0d, 0x01100000, 0x512c0040, 0xf006f19f,
+	0xf0061a10, 0x7006ca04, 0x9fa5ca00, 0x9e972fa0, 0x00200040, 0xb62c6a0d,
+	0x01100000, 0x4e0651ac, 0x40801624, 0x20d8831c, 0x040d51a8, 0x4e061820,
+	0xf19f7620, 0x00a03846, 0x1100580c, 0xdea1c045, 0xccfb1f17, 0xc4300000,
+	0xf1a5c6a5, 0x61140011, 0x81890300, 0x890401a8, 0x51bc11f4, 0x06210040,
+	0x03c30000, 0x43920000, 0x84f91f17, 0xb480690d, 0x86ff1f1e, 0x81890300,
+	0x890401a8, 0x51bc11f4, 0x74210040, 0x83610000, 0x70210040, 0x23490000,
+	0x000c01a8, 0x91bb1110, 0x71bfb1a5, 0xecf71f17, 0x00a0c949, 0xa4f71f1f,
+	0xb2246408, 0x00a0f84c, 0xe1a511ac, 0x90fe1f17, 0x13701e04, 0xb2f71f17,
+	0x10acc949, 0x7cf71f1f, 0x4cf81f17, 0x00a0414c, 0xf00146a8, 0x618a0100,
+	0x41a841b4, 0x618be6a5, 0x41a841b4, 0x41b4c081, 0xc6a541a8, 0x11060320,
+	0x030041b6, 0x01a88189, 0x1108000c, 0x20dc821d, 0x80d88215, 0xd3a50a4c,
+	0x68fb1f17, 0xc4300000, 0xf1a5c6a5, 0x61140011, 0x81890300, 0x890401a8,
+	0x51bc11f4, 0x06210040, 0x03c30000, 0x43920000, 0x20f91f17, 0xb480690d,
+	0x50ff1f1e, 0x81890300, 0x890401a8, 0x51bc11f4, 0x74210040, 0x83610000,
+	0x70210040, 0x23490000, 0x98040013, 0x02931298, 0xe6fe1f1e, 0x31a70e92,
+	0x0100300f, 0x11306a0d, 0x53a742a7, 0x75a764a7, 0x97a786a7, 0xb9a7a8a7,
+	0xdba7caa7, 0xfda7eca7, 0x01a82fa7, 0x11e88904, 0x2048801c, 0x0100300f,
+	0x1140600d, 0x408001a8, 0x300fa1bd, 0x610d0100, 0x00a01120, 0x831506a8,
+	0x0b0fc0fe, 0x300f0616, 0x60080100, 0x000d1148, 0xf006660c, 0x47066109,
+	0x890461ff, 0x7706669d, 0x00a061ff, 0x40fe1f1f, 0x0100300f, 0x11306d08,
+	0xf60f0000, 0x2fa506ac, 0x42a531a5, 0x64a553a5, 0x86a575a5, 0xa8a597a5,
+	0xcaa5b9a5, 0xeca5dba5, 0x2e97fda5, 0x0000a005, 0x47f00049, 0x3870b149,
+	0xffa7a949, 0x61288249, 0x1f1700c9, 0x61b4abf8, 0xc46461a8, 0x1f170020,
+	0x61b6a5f8, 0x71a89149, 0x11b78904, 0x71a871b4, 0x1f1700c9, 0x71b49bf8,
+	0x890471a8, 0x71b61197, 0x2fa0ffa5, 0x0080fe97, 0x300f0192, 0x60080100,
+	0xf0001134, 0x0b0f0600, 0x000d0716, 0xffa77908, 0x6110f006, 0x8a860300,
+	0x09ac89b4, 0x1a004006, 0x1102000c, 0x500fa1bb, 0xc30d0d00, 0xc30dd44c,
+	0x0000d340, 0x1f178620, 0xa599bdff, 0x0600300f, 0x6650680d, 0xd304cf0d,
+	0x50f71f17, 0x00208249, 0x8c6451a8, 0x51b60020, 0x06800000, 0xedf3f19c,
+	0x28c9618a, 0x06800000, 0x4006c5f2, 0x40801a00, 0x030021bb, 0x500fc688,
+	0x100d0100, 0x0c4c1170, 0x89040728, 0x07b67796, 0x11b4ef08, 0x06b656a8,
+	0x08360040, 0x0200300f, 0x22f4640d, 0x87890300, 0x11a8314c, 0xf49f08c9,
+	0x1258f306, 0x986411a8, 0x1f170020, 0x11ac2bf7, 0x890461a8, 0x1f17119e,
+	0x61b6ddf6, 0x12e0c106, 0x580c418c, 0x000d1100, 0xf8061190, 0x7e061200,
+	0x7e064208, 0x7e069218, 0xffa5921c, 0xfe972fa0, 0x00800080, 0x0100500f,
+	0x12a01208, 0xfda59849, 0x11b5e3a5, 0x426cf406, 0x5270f406, 0x6220f006,
+	0x7214f006, 0x8215fa06, 0x92077d06, 0xa2ff7706, 0xd2f77c06, 0xfef71f16,
+	0x00800493, 0x0100500f, 0x12a41208, 0xfda59849, 0x11b5e3a5, 0x426cf406,
+	0x5270f406, 0x6220f006, 0x7214f006, 0x8215fa06, 0x92077d06, 0xa2ff7706,
+	0xd2f77c06, 0xe2f71f16, 0x00800493, 0x0101500f, 0x3cf00149, 0x11042008,
+	0xdfa78d49, 0xc6860300, 0x81880300, 0x0bfcff06, 0x5328f94f, 0x04a81146,
+	0xc1870300, 0x05a8248c, 0x41890300, 0x06a8258c, 0x01890300, 0x07a8268c,
+	0x41860300, 0x08a8278c, 0x01860300, 0x09a8288c, 0x41870300, 0x0aa8298c,
+	0x01870300, 0x01a82a8c, 0x00a01046, 0x0000f1a7, 0x1f17e105, 0xe1a7b1ff,
+	0x1b004006, 0x100040c9, 0xf0060600, 0x40061b00, 0x08c91b00, 0x0700800f,
+	0x1bf0ff06, 0x01800000, 0x61640007, 0x5ef61f17, 0x71640007, 0x01ffdf0f,
+	0x115c480d, 0x06a8b188, 0x06b6c68b, 0x2fa0dfa5, 0x0080de97, 0x0b0f0492,
+	0x000d0716, 0x300f7708, 0x60080c00, 0xf000c134, 0xcfa70600, 0xf006f7a7,
+	0x87b46110, 0x440607ac, 0x000c11ac, 0x801c1102, 0x00a0220a, 0xdefe1f1f,
+	0x81860300, 0x01280040, 0x11f48904, 0x20cc811c, 0x81890300, 0x01a8e1a7,
+	0x11f68904, 0x00a021bf, 0xd2f81f17, 0xc3bc630d, 0xcef81f17, 0xc3b8630d,
+	0x0100300f, 0x114c680d, 0x890406a8, 0x06b66696, 0x0800300f, 0x884c680d,
+	0xf86471a8, 0x71b40020, 0x01a8e1a5, 0x1104000c, 0x202c811c, 0x01a8e1a5,
+	0x11f08904, 0x00a0a1be, 0xaef81f17, 0xc36c630d, 0x890471a8, 0x71b61190,
+	0x0600300f, 0x66dc600d, 0x51a80399, 0xf30690c9, 0x200f16d0, 0x2e0d0121,
+	0x61881160, 0x51a8d1a7, 0x1f1788c9, 0x51ac41ff, 0xd1a5214c, 0x01a81693,
+	0xd2258464, 0x51a851ac, 0xf00688c9, 0x11a81248, 0x11ac08c9, 0x88c911a8,
+	0x1248f006, 0x08c911a8, 0x11a811ac, 0xf00688c9, 0x11a81240, 0x11ac08c9,
+	0x88c911a8, 0x1230f006, 0x08c911a8, 0x11a811ac, 0xf00688c9, 0x11a81248,
+	0x11ac08c9, 0x88c911a8, 0x1250f006, 0x08c911a8, 0x11a811ac, 0xf00688c9,
+	0x11a81270, 0x11ac08c9, 0x88c911a8, 0x1200fe06, 0xf006f19f, 0xf0061248,
+	0xf0061248, 0xf006123c, 0xf0061234, 0xf0061248, 0xf0061250, 0x1f171270,
+	0x11acc9f5, 0x01dedf0f, 0x1110d50d, 0xe1250944, 0x00208b49, 0x890401a8,
+	0x1f17119f, 0x51b673f5, 0x62204e06, 0x618cf19f, 0x1100580c, 0x1120050d,
+	0x1200f806, 0x7e06f19f, 0xf1a51208, 0x12187e06, 0x121c7e06, 0x2fa0cfa5,
+	0x0080ce97, 0xdcfb1f17, 0x00a0094c, 0x0723500f, 0x773c850d, 0x890461a8,
+	0x100016b8, 0x66b40101, 0x890466a8, 0xff0f6299, 0x4b0d06dc, 0x62b66604,
+	0x590f7188, 0x02a80700, 0x22b88904, 0x7700800d, 0x02a802b4, 0x22998904,
+	0x168802b6, 0x178b51a8, 0x1f1657b6, 0x51aa45ff, 0xf6f71f17, 0xc384630d,
+	0xf2f71f17, 0xc388630d, 0xeef71f17, 0xc38c630d, 0xeaf71f17, 0xc3a0630d,
+	0xe6f71f17, 0xc380630d, 0x08ff1f1e, 0x0b0f0692, 0x300f0616, 0x000d0100,
+	0x60086608, 0xf0001c34, 0xafa70100, 0xf006d6a7, 0xf0061c10, 0xf0066c04,
+	0x40066cf4, 0x000c1c00, 0x01151110, 0x10000107, 0x300f0600, 0x660d0100,
+	0x7c4c117c, 0x0000c127, 0x800f0180, 0x00070700, 0x00006165, 0x00a0eb05,
+	0x10f51f17, 0x71650007, 0xf8278549, 0xeb278449, 0x09400100, 0x05060000,
+	0x13120000, 0x07708249, 0x1afe1f17, 0x06700040, 0x01e0000f, 0xeba78449,
+	0xf0278349, 0x1340000d, 0x0700300f, 0x0cfe1f17, 0x04f08249, 0x01a8c1a5,
+	0x80144080, 0xc1a52056, 0x01a81793, 0x16000f0c, 0x81980b00, 0x119d8904,
+	0xbca73844, 0x66641c04, 0x61a806ac, 0x677c4e06, 0x22204081, 0x00196620,
+	0x00a06115, 0x01a8b1a5, 0x11e88904, 0x00a041bc, 0x6efb1f1f, 0x1693c1a5,
+	0x4e0601a8, 0x4081667c, 0x66202220, 0x16f07f1b, 0x91002800, 0x0300d191,
+	0x06a88286, 0x06b48dc9, 0xc5c906a8, 0x11a806b6, 0x11f88904, 0x300f81be,
+	0x600d0100, 0x06a811dc, 0x06b615c9, 0x85890300, 0x890441a8, 0xf1ba11f0,
+	0x0100300f, 0x30f71f17, 0x136c630d, 0x0100300f, 0x114c680d, 0xbe6406a8,
+	0x06b600a0, 0x41280040, 0x1104000c, 0x20a08014, 0x0100590f, 0x890411a8,
+	0xf1bb11f4, 0x0100300f, 0x16f71f17, 0x1384630d, 0x0100300f, 0x10f71f17,
+	0x1388630d, 0x0100300f, 0x0af71f17, 0x138c630d, 0x0100300f, 0x04f71f17,
+	0x13a0630d, 0x0100300f, 0xfef61f17, 0x1380630d, 0x0400300f, 0x444c680d,
+	0xf94f5398, 0x94643128, 0x1f170020, 0x31ac8bf4, 0x890441a8, 0x41b411bf,
+	0x890441a8, 0x1f17119b, 0x41b639f4, 0x14e0c106, 0x580c218c, 0x000d1100,
+	0xf8061190, 0xd1a51400, 0x24087e06, 0x14187e06, 0x141c7e06, 0x2fa0afa5,
+	0x0080ae97, 0x0700500f, 0x7730d00d, 0x66a8414c, 0x618bfdc9, 0x76d48a00,
+	0x61369348, 0x10007688, 0x57a80101, 0x77b98904, 0x57a857b4, 0x77988904,
+	0x304457b6, 0x06a800a0, 0x66b98904, 0x06a806b4, 0x66988904, 0x1f1706b6,
+	0x01aa83fa, 0x90ff1f1e, 0x2fa0afa5, 0x0080ae97, 0x300f0392, 0x60080100,
+	0xf0001134, 0x0b0f0700, 0x000d0816, 0xdfa78b08, 0x7110f006, 0x86860300,
+	0x0bac8bb4, 0x890451a8, 0x91b811ff, 0x0100300f, 0x13c0630d, 0x42fa1f17,
+	0x0020024d, 0x8c890300, 0x1c004006, 0x1102000c, 0x20b48014, 0x0100300f,
+	0x1c004006, 0x1100800c, 0x000021b9, 0x500f83a2, 0xc00d0101, 0x82491114,
+	0xb2640628, 0x06b500a0, 0x300d06a8, 0x1f176600, 0x06b60df5, 0x00208249,
+	0x08f51f17, 0x03450100, 0x0100300f, 0x9ef61f17, 0x13b0630d, 0x0800500f,
+	0x81c41008, 0x0600040f, 0x0200e00f, 0x2230540d, 0x062c0944, 0xfa4f2398,
+	0x00c91128, 0x1258f306, 0x886411a8, 0x1f170020, 0x11ace1f3, 0x1c004006,
+	0x119d8904, 0x92f31f17, 0x1cf0ff06, 0x12e0c106, 0x580c418c, 0x000d1100,
+	0xf8061158, 0x7e061200, 0x7e064208, 0x7e06b218, 0xdfa5b21c, 0xde972fa0,
+	0x00200040, 0x12946308, 0x21ff0000, 0x0600300f, 0x12bcf406, 0x6324630d,
+	0xa2f91f17, 0x0a70024d, 0x0100300f, 0x13a4630d, 0x9af91f17, 0x0970024d,
+	0x1128824c, 0x034d30c9, 0x190ff4a7, 0x000f0813, 0x11ac0d80, 0x720de7a7,
+	0x0a0d8398, 0x0000d600, 0x000f1508, 0xc00f0460, 0x1f170700, 0x08f0a5fc,
+	0x7cff1f1e, 0x03000192, 0xffa78189, 0x890401a8, 0x51bb11f2, 0x0700300f,
+	0x00208249, 0x8ef41f17, 0xe3040000, 0xc2f31f17, 0x73c0630d, 0x0100300f,
+	0x114c680d, 0x890406a8, 0x06b66691, 0x0100300f, 0x114c680d, 0x5dc906a8,
+	0x61e0f106, 0xddc906a8, 0xffa506ac, 0xfe972fa0, 0x00800080, 0x300f0192,
+	0x60080100, 0xf0001134, 0x0b0f0600, 0x000d0716, 0xffa77508, 0x6110f006,
+	0x05ac85b4, 0x11f44006, 0x1140000c, 0xffa561b8, 0xfe972fa0, 0x00200040,
+	0x0100300f, 0x11f4640d, 0x88860300, 0x8dc906a8, 0x71a806b6, 0xd1ba4080,
+	0x0100500f, 0x1798f698, 0x12701008, 0x87ac06af, 0x890411a8, 0x11ac11b6,
+	0x06800000, 0xedf3f19c, 0x20c9618a, 0x06800000, 0x0200300f, 0x224c680d,
+	0x11a8c5f2, 0x11eb8904, 0x00a041be, 0x90ff1f1f, 0x000c71a8, 0x71bb1102,
+	0x0700500f, 0x7304cf0d, 0x08f31f17, 0x00200a4c, 0x0600300f, 0x6650680d,
+	0x744cc30d, 0x04f31f17, 0x7340c30d, 0x886451a8, 0x51b60020, 0x11a8394c,
+	0x00209c64, 0x87890300, 0x00f31f17, 0x112cfa4f, 0x890461a8, 0x1f1711be,
+	0x61b6b1f2, 0x12e0c106, 0x580c418c, 0x000d1100, 0xf8061158, 0x7e061200,
+	0x7e064208, 0x7e065218, 0xffa5521c, 0xfe972fa0, 0x00800080, 0x03000192,
+	0xffa78189, 0x890401a8, 0x51bb11f1, 0x0700300f, 0x00208249, 0xdef31f17,
+	0xe3040000, 0x38f51f17, 0x7374630d, 0x0100300f, 0x114c680d, 0x890406a8,
+	0x06b66693, 0x0100300f, 0x114c680d, 0x65c906a8, 0x61e0f106, 0xe5c906a8,
+	0xffa506ac, 0xfe972fa0, 0x00800080, 0x03000192, 0xffa78189, 0x890401a8,
+	0x31bb11f6, 0x0200300f, 0x12f51f17, 0x23b8630d, 0x0ef51f17, 0x23bc630d,
+	0x0100300f, 0x114c680d, 0x890406a8, 0x06b66695, 0x0100300f, 0x114c680d,
+	0x75c906a8, 0x61e0f106, 0xf5c906a8, 0xffa506ac, 0xfe972fa0, 0x00800080,
+	0x300f0592, 0x60080b00, 0xf000b134, 0x0b0f0600, 0x000d0716, 0xbfa77c08,
+	0x6110f006, 0x0cac8cb4, 0x11f44006, 0x1104000c, 0xbfa561b8, 0xbe972fa0,
+	0x00200040, 0x0100300f, 0x11f4640d, 0x85c906a8, 0x030006b6, 0xd1a78189,
+	0x800c01a8, 0xd1b81100, 0xf6fffc01, 0x0701500f, 0x7714c00d, 0x618a61a8,
+	0x61a861b5, 0x66b6168a, 0x0100500f, 0x12c01008, 0xbaf41f17, 0xb3b0630d,
+	0x0500040f, 0x15acd1a5, 0x01280040, 0x1102000c, 0x2078801c, 0x81860300,
+	0x890401a8, 0xd1bc11ff, 0x4af21f17, 0xb3c0630d, 0x0100300f, 0x110c660d,
+	0x890406a8, 0x06b6669f, 0x0200300f, 0x224c680d, 0xfa4f3398, 0x8c641128,
+	0x1f170020, 0x11ac2bf2, 0x1693d1a5, 0x890401a8, 0x1f1711bd, 0x51b6dbf1,
+	0x12e0c106, 0x580c418c, 0x000d1100, 0xf8061106, 0x7e061200, 0x7e064208,
+	0x7e06c218, 0xbfa5c21c, 0xbe972fa0, 0x00200040, 0x0200300f, 0x224c680d,
+	0x890411a8, 0x31be11ec, 0x22ff1f1f, 0x890411a8, 0x31be11ee, 0x48ff1f1f,
+	0x08100000, 0x0113190f, 0x8ff3864c, 0x22b58904, 0x1398320d, 0xb1306d08,
+	0xf50f0000, 0x8f728549, 0x5120fb06, 0xc1a7004d, 0xfda78449, 0xe1278449,
+	0x0700800f, 0x0680000f, 0x0420000f, 0xd0fa1f17, 0x00a00a4c, 0xf0a7004d,
+	0x0700400f, 0xe1270040, 0x05080000, 0x06a00000, 0x0440000f, 0xc0fa1f17,
+	0x03000400, 0xe4f11f17, 0xb3a4630d, 0x01ff000f, 0x16f20f0d, 0xdcf11f17,
+	0xb324630d, 0x7b06c1a5, 0x01a86144, 0xc6259464, 0x72ff1f16, 0x008051ac,
+	0x0100400f, 0x05700449, 0x1c01000d, 0x81890300, 0x8fa7714c, 0xf1270040,
+	0x0100300f, 0x19b06008, 0xe0f41f17, 0x44100000, 0x099cf706, 0x19304e06,
+	0xe9278040, 0x11771e04, 0x0b00f00f, 0x1f0f1b8b, 0x990d0dff, 0xf006ddd0,
+	0xf006b904, 0xf1a5c904, 0xc6880300, 0xe00f01a8, 0x530d0a00, 0xfd06aa10,
+	0xd9a719e0, 0x0904f006, 0x0904f006, 0x0904f006, 0x70069d88, 0x40060900,
+	0x00811d00, 0xd7001708, 0x512c3d44, 0x17104b06, 0xc6860300, 0x4b0651ac,
+	0x03001740, 0x51ac8688, 0x030061a8, 0x51acc687, 0x17704406, 0x46890300,
+	0x440651ac, 0x03001790, 0x51ac0689, 0x17a44406, 0x46860300, 0x4b0651ac,
+	0x030017c0, 0x51ac0686, 0x17b84606, 0x46870300, 0x4b0651ac, 0x030017b0,
+	0xf84f0687, 0xfe0651ac, 0xf1a51a30, 0x01a8caa7, 0x11f38904, 0x500fa1bc,
+	0x1b0d0100, 0x06a811c8, 0x6605000d, 0x06360040, 0x01a8f1a5, 0x1100010c,
+	0x000081ba, 0x01000180, 0x00070600, 0x00a06165, 0x01a8f1a5, 0x1100020c,
+	0x510fa1b9, 0x0b000600, 0x3044c103, 0x000000a0, 0x000fe710, 0xcd0d0626,
+	0xf1066600, 0xf1067100, 0xf1067100, 0x0b447100, 0xf106072c, 0xf1067600,
+	0x57ac7600, 0x0100300f, 0x162c6a08, 0x01d20500, 0x020fb6a7, 0xf2060716,
+	0x7f0d16d4, 0xf1a577d8, 0x01a857ac, 0x11f78904, 0x000f61ba, 0x57a80116,
+	0x51ac718b, 0x0100300f, 0x11306a0d, 0x0694010f, 0xa1270040, 0x01100000,
+	0x03400000, 0x20f71f17, 0x61650007, 0x01100000, 0x890480f3, 0x011511f2,
+	0xd1a5010b, 0x011501a8, 0xc1a50107, 0x890401a8, 0x011511e8, 0x00000101,
+	0x80f30110, 0x11f38904, 0x20988115, 0xa1250040, 0x01100000, 0x80730040,
+	0x11f48904, 0x20548115, 0x01800000, 0x01100000, 0x890480f3, 0x801511f5,
+	0xa1a520c2, 0x01100000, 0x890480f3, 0xd1bb11f6, 0xa1250040, 0x01800000,
+	0x06800400, 0x00008005, 0x61640007, 0x01a8f1a5, 0x11fc8904, 0x0000c1ba,
+	0x784e0180, 0x618ae8f3, 0x000020c9, 0x1f170680, 0xc5f25bf5, 0xb4ff1f1e,
+	0x91a701a8, 0x1120000c, 0x20688015, 0x040c91a5, 0x80151100, 0x91a52056,
+	0x1180000c, 0x20448015, 0x000c91a5, 0x51bc1108, 0x00200040, 0xf2fd1f1f,
+	0x01100000, 0x08100000, 0x890480f3, 0x300f11b6, 0x97a50600, 0x6d0887f2,
+	0x00006630, 0x000cf10f, 0x51ac7702, 0xe078831c, 0xf4f31f1f, 0xb8ff1f1e,
+	0xfefc1f1f, 0xe6210040, 0xc0f01f1f, 0xe2210040, 0xfafa1f1f, 0xde210040,
+	0x080c01a8, 0x96bc1600, 0x0600300f, 0x6660660d, 0x6d8056a8, 0xc064801d,
+	0x1600100c, 0x300fa6bc, 0x660d0600, 0x56a86660, 0x6602000c, 0xc244801c,
+	0x1100400c, 0x300fc1bc, 0x610d0100, 0x01a8116c, 0x1100080c, 0x00a041be,
+	0x7efd1f1f, 0x01100000, 0x07100000, 0x890480f3, 0x300f11b5, 0x86f20600,
+	0x66306d08, 0xf10f0000, 0x6eff1f16, 0x512c0040, 0x3efd1f1f, 0xec210040,
+	0x8afc1f1f, 0xe8210040, 0x8904c0f3, 0x31bc11f0, 0x8ef61f1f, 0x01100000,
+	0x07100000, 0x890480f3, 0x300f11b4, 0x86f20600, 0x66306d08, 0xf10f0000,
+	0x46ff1f16, 0x512c0040, 0x020c01a8, 0x80151600, 0x000cc04e, 0xf6bb1610,
+	0x1640000c, 0x000c86bf, 0x31bc1104, 0xb2fb1f1f, 0x01100000, 0x07100000,
+	0x890480f3, 0x300f11b3, 0x86f20600, 0x66306d08, 0xf10f0000, 0x1aff1f16,
+	0x512c0040, 0x56f81f1f, 0xec210040, 0x5cf91f1f, 0xe8210040, 0x20f01f1f,
+	0xe4210040, 0x01a8f1a5, 0x11fd8904, 0x00a041be, 0x8cfb1f1f, 0x01a8f1a5,
+	0x11f28904, 0x300fe1ba, 0x00a00100, 0x96f21f17, 0x13c0630d, 0x01a8e1a5,
+	0x16928904, 0x06ace1a5, 0x01a8f1a5, 0x11f18904, 0x300fe1ba, 0x00a00100,
+	0x54f21f17, 0x1374630d, 0x01a8e1a5, 0x16948904, 0x06ace1a5, 0x01a8f1a5,
+	0x11fe8904, 0x00a041be, 0x18f81f1f, 0x01a8f1a5, 0x11fb8904, 0x00a041be,
+	0xe2ef1f1f, 0x01a8f1a5, 0x11ff8904, 0x00a041be, 0x12f91f1f, 0x01a8c1a5,
+	0x11ff8904, 0x4c0f61b8, 0x0b4c0156, 0x06ac0020, 0x01564c0f, 0x0600a000,
+	0x0700800f, 0x080a800f, 0x87af06af, 0x082f0040, 0xb2f51f17, 0x03800000,
+	0x0794010f, 0x01100000, 0x86000400, 0x71640007, 0x07100000, 0xf206b1a5,
+	0xf00671d4, 0x00006130, 0xadf30610, 0x66b38904, 0x0000aef2, 0x06acf60f,
+	0x06100000, 0x8904adf3, 0xaef266b6, 0xf60f0000, 0x000006ac, 0xadf30610,
+	0x66b58904, 0x0000aef2, 0x06acf60f, 0x01a8f1a5, 0x11f38904, 0x500fc1bc,
+	0x1b0d0100, 0x06a811cc, 0x86b715c9, 0x866406a8, 0x06b600a0, 0x0100300f,
+	0x1140610d, 0x61fcc406, 0x4a0686b4, 0xf30661e0, 0xfa0661ec, 0x7c060100,
+	0x06a80184, 0x06ac0dc9, 0x01a8f1a5, 0x1100020c, 0x20c8801c, 0x0100510f,
+	0x113cb00d, 0x040c01a8, 0x71ba1181, 0x0600510f, 0xc1030b00, 0x00ac6188,
+	0x0100510f, 0x113cb10d, 0x040c01a8, 0x71ba1181, 0x0600510f, 0xc1130b00,
+	0x00ac6188, 0x0100510f, 0x113cb20d, 0x040c01a8, 0x71ba1181, 0x0600510f,
+	0xc1230b00, 0x00ac6188, 0x0100510f, 0x113cb30d, 0x040c01a8, 0x71ba1181,
+	0x0600510f, 0xc1330b00, 0x00ac6188, 0x0127510f, 0x113c800d, 0x040c01a8,
+	0x71ba1181, 0x0627510f, 0xc1030800, 0x00ac6188, 0x0127510f, 0x113c810d,
+	0x040c01a8, 0x71ba1181, 0x0627510f, 0xc1130800, 0x00ac6188, 0x0127510f,
+	0x113c820d, 0x040c01a8, 0x71ba1181, 0x0627510f, 0xc1230800, 0x00ac6188,
+	0x00000593, 0x1f174410, 0xf398f9f1, 0x1f168fa5, 0x8e97ebf0, 0x801d43bc,
+	0x00a06112, 0x01800000, 0x0600020f, 0x68720040, 0x81890300, 0x040c01a8,
+	0x31be1100, 0x3f200040, 0x6608801d, 0x3f200040, 0x6708801d, 0x3f200040,
+	0x00002fa0, 0x80f20180, 0x0100300f, 0x11746408, 0xf6af0000, 0x07cccc0f,
+	0x77cccc0d, 0xf0062fa0, 0x07ac6128, 0x09800000, 0x00a00049, 0x0700300f,
+	0x77a0640d, 0x19400007, 0x8904ffa7, 0x61a81afe, 0xc6ff1f17, 0x13082120,
+	0x0800040f, 0x0200100f, 0x0400080f, 0x200fcab8, 0x00070500, 0x00078962,
+	0x00072962, 0x0ba14961, 0x59610007, 0x89610007, 0x29610007, 0x49620007,
+	0x59620007, 0x1c0d61a8, 0x05001100, 0x61b606bc, 0x619d8904, 0xff017188,
+	0x07a8b67f, 0xff0f768a, 0x86b407ef, 0x76fff70d, 0x768a07a8, 0xffa506b6,
+	0xfe972fa0, 0x00800080, 0xcfa70492, 0x78ef1f1f, 0xb6ff1f1f, 0xa6ff1f1f,
+	0x81890300, 0x0300f1a7, 0xe1a78186, 0x01800000, 0x06200000, 0x61640007,
+	0x01100000, 0x0694010f, 0x61650007, 0x01160b0f, 0x0600300f, 0x110c000d,
+	0x66446008, 0x400651ac, 0x831576dc, 0x010fe0fa, 0x300f0794, 0x60080600,
+	0x51ac6648, 0x01100000, 0x71640007, 0x16b84506, 0x61acf7a5, 0x16c04506,
+	0x51b4e6a5, 0x66a8d6a7, 0x0100f80f, 0x1f17618b, 0x61acbded, 0x01a8f1a5,
+	0x1100040c, 0x00a041be, 0x48fc1f1f, 0x01a8f1a5, 0x1100040c, 0xf1a581b8,
+	0x000c01a8, 0x31be1120, 0x66ee1f1f, 0x01a8d1a5, 0x1140000c, 0x20688314,
+	0x0600800f, 0x07800000, 0xcfa58049, 0x67670007, 0x3f20e74b, 0x01000100,
+	0x01000201, 0x02010201, 0x01000402, 0x02010402, 0x04020402, 0x01000803,
+	0x02010803, 0x04020803, 0x01001004, 0x02011004, 0x04021004, 0x08031004,
+	0x01002005, 0x02012005, 0x04022005, 0x08032005, 0x01004006, 0x02014006,
+	0x04024006, 0x08034006
+};
+
+static struct spm_desc spm_firmware = {
+	.version = "pcm_suspend_v1.43_no_GPU_WAYEN",
+	.pmem_words = 0x9bf,
+	.total_words = 0x9d4,
+	.pmem_start = 0x10000000,
+	.dmem_start = 0x10003800
+};
+
+static struct pwr_ctrl spm_init_ctrl = {
+	/* Auto-gen Start */
+
+	.pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS |
+		     SPM_FLAG_RUN_COMMON_SCENARIO,
+
+	/* SPM_AP_STANDBY_CON */
+	.reg_wfi_op = 0,
+	.reg_wfi_type = 0,
+	.reg_mp0_cputop_idle_mask = 0,
+	.reg_mp1_cputop_idle_mask = 0,
+	.reg_mcusys_idle_mask = 0,
+	.reg_md_apsrc_1_sel = 0,
+	.reg_md_apsrc_0_sel = 0,
+	.reg_conn_apsrc_sel = 0,
+
+	/* SPM_SRC6_MASK */
+	.reg_dpmaif_srcclkena_mask_b = 1,
+	.reg_dpmaif_infra_req_mask_b = 1,
+	.reg_dpmaif_apsrc_req_mask_b = 1,
+	.reg_dpmaif_vrf18_req_mask_b = 1,
+	.reg_dpmaif_ddr_en_mask_b    = 1,
+
+	/* SPM_SRC_REQ */
+	.reg_spm_apsrc_req = 0,
+	.reg_spm_f26m_req = 0,
+	.reg_spm_infra_req = 0,
+	.reg_spm_vrf18_req = 0,
+	.reg_spm_ddr_en_req = 1,
+	.reg_spm_dvfs_req = 0,
+	.reg_spm_sw_mailbox_req = 0,
+	.reg_spm_sspm_mailbox_req = 0,
+	.reg_spm_adsp_mailbox_req = 0,
+	.reg_spm_scp_mailbox_req = 0,
+
+	/* SPM_SRC_MASK */
+	.reg_md_srcclkena_0_mask_b = 1,
+	.reg_md_srcclkena2infra_req_0_mask_b = 0,
+	.reg_md_apsrc2infra_req_0_mask_b = 1,
+	.reg_md_apsrc_req_0_mask_b = 1,
+	.reg_md_vrf18_req_0_mask_b = 1,
+	.reg_md_ddr_en_0_mask_b = 1,
+	.reg_md_srcclkena_1_mask_b = 0,
+	.reg_md_srcclkena2infra_req_1_mask_b = 0,
+	.reg_md_apsrc2infra_req_1_mask_b = 0,
+	.reg_md_apsrc_req_1_mask_b = 0,
+	.reg_md_vrf18_req_1_mask_b = 0,
+	.reg_md_ddr_en_1_mask_b = 0,
+	.reg_conn_srcclkena_mask_b = 1,
+	.reg_conn_srcclkenb_mask_b = 0,
+	.reg_conn_infra_req_mask_b = 1,
+	.reg_conn_apsrc_req_mask_b = 1,
+	.reg_conn_vrf18_req_mask_b = 1,
+	.reg_conn_ddr_en_mask_b = 1,
+	.reg_conn_vfe28_mask_b = 0,
+	.reg_srcclkeni0_srcclkena_mask_b = 1,
+	.reg_srcclkeni0_infra_req_mask_b = 1,
+	.reg_srcclkeni1_srcclkena_mask_b = 0,
+	.reg_srcclkeni1_infra_req_mask_b = 0,
+	.reg_srcclkeni2_srcclkena_mask_b = 0,
+	.reg_srcclkeni2_infra_req_mask_b = 0,
+	.reg_infrasys_apsrc_req_mask_b = 0,
+	.reg_infrasys_ddr_en_mask_b = 1,
+	.reg_md32_srcclkena_mask_b = 1,
+	.reg_md32_infra_req_mask_b = 1,
+	.reg_md32_apsrc_req_mask_b = 1,
+	.reg_md32_vrf18_req_mask_b = 1,
+	.reg_md32_ddr_en_mask_b = 1,
+
+	/* SPM_SRC2_MASK */
+	.reg_scp_srcclkena_mask_b = 1,
+	.reg_scp_infra_req_mask_b = 1,
+	.reg_scp_apsrc_req_mask_b = 1,
+	.reg_scp_vrf18_req_mask_b = 1,
+	.reg_scp_ddr_en_mask_b = 1,
+	.reg_audio_dsp_srcclkena_mask_b = 1,
+	.reg_audio_dsp_infra_req_mask_b = 1,
+	.reg_audio_dsp_apsrc_req_mask_b = 1,
+	.reg_audio_dsp_vrf18_req_mask_b = 1,
+	.reg_audio_dsp_ddr_en_mask_b = 1,
+	.reg_ufs_srcclkena_mask_b = 1,
+	.reg_ufs_infra_req_mask_b = 1,
+	.reg_ufs_apsrc_req_mask_b = 1,
+	.reg_ufs_vrf18_req_mask_b = 1,
+	.reg_ufs_ddr_en_mask_b = 1,
+	.reg_disp0_apsrc_req_mask_b = 1,
+	.reg_disp0_ddr_en_mask_b = 1,
+	.reg_disp1_apsrc_req_mask_b = 1,
+	.reg_disp1_ddr_en_mask_b = 1,
+	.reg_gce_infra_req_mask_b = 1,
+	.reg_gce_apsrc_req_mask_b = 1,
+	.reg_gce_vrf18_req_mask_b = 1,
+	.reg_gce_ddr_en_mask_b = 1,
+	.reg_apu_srcclkena_mask_b = 1,
+	.reg_apu_infra_req_mask_b = 1,
+	.reg_apu_apsrc_req_mask_b = 1,
+	.reg_apu_vrf18_req_mask_b = 1,
+	.reg_apu_ddr_en_mask_b = 1,
+	.reg_cg_check_srcclkena_mask_b = 0,
+	.reg_cg_check_apsrc_req_mask_b = 0,
+	.reg_cg_check_vrf18_req_mask_b = 0,
+	.reg_cg_check_ddr_en_mask_b = 0,
+
+	/* SPM_SRC3_MASK */
+	.reg_dvfsrc_event_trigger_mask_b = 1,
+	.reg_sw2spm_int0_mask_b = 0,
+	.reg_sw2spm_int1_mask_b = 0,
+	.reg_sw2spm_int2_mask_b = 0,
+	.reg_sw2spm_int3_mask_b = 0,
+	.reg_sc_adsp2spm_wakeup_mask_b = 0,
+	.reg_sc_sspm2spm_wakeup_mask_b = 0,
+	.reg_sc_scp2spm_wakeup_mask_b = 0,
+	.reg_csyspwrreq_mask = 1,
+	.reg_spm_srcclkena_reserved_mask_b = 0,
+	.reg_spm_infra_req_reserved_mask_b = 0,
+	.reg_spm_apsrc_req_reserved_mask_b = 0,
+	.reg_spm_vrf18_req_reserved_mask_b = 0,
+	.reg_spm_ddr_en_reserved_mask_b = 0,
+	.reg_mcupm_srcclkena_mask_b = 1,
+	.reg_mcupm_infra_req_mask_b = 1,
+	.reg_mcupm_apsrc_req_mask_b = 1,
+	.reg_mcupm_vrf18_req_mask_b = 1,
+	.reg_mcupm_ddr_en_mask_b = 1,
+	.reg_msdc0_srcclkena_mask_b = 1,
+	.reg_msdc0_infra_req_mask_b = 1,
+	.reg_msdc0_apsrc_req_mask_b = 1,
+	.reg_msdc0_vrf18_req_mask_b = 1,
+	.reg_msdc0_ddr_en_mask_b = 1,
+	.reg_msdc1_srcclkena_mask_b = 1,
+	.reg_msdc1_infra_req_mask_b = 1,
+	.reg_msdc1_apsrc_req_mask_b = 1,
+	.reg_msdc1_vrf18_req_mask_b = 1,
+	.reg_msdc1_ddr_en_mask_b = 1,
+
+	/* SPM_SRC4_MASK */
+	.ccif_event_mask_b = 0xFFF,
+	.reg_bak_psri_srcclkena_mask_b = 0,
+	.reg_bak_psri_infra_req_mask_b = 0,
+	.reg_bak_psri_apsrc_req_mask_b = 0,
+	.reg_bak_psri_vrf18_req_mask_b = 0,
+	.reg_bak_psri_ddr_en_mask_b = 0,
+	.reg_dramc0_md32_infra_req_mask_b = 1,
+	.reg_dramc0_md32_vrf18_req_mask_b = 0,
+	.reg_dramc1_md32_infra_req_mask_b = 1,
+	.reg_dramc1_md32_vrf18_req_mask_b = 0,
+	.reg_conn_srcclkenb2pwrap_mask_b = 0,
+	.reg_dramc0_md32_wakeup_mask = 1,
+	.reg_dramc1_md32_wakeup_mask = 1,
+
+	/* SPM_SRC5_MASK */
+	.reg_mcusys_merge_apsrc_req_mask_b = 0x11,
+	.reg_mcusys_merge_ddr_en_mask_b = 0x11,
+	.reg_msdc2_srcclkena_mask_b = 1,
+	.reg_msdc2_infra_req_mask_b = 1,
+	.reg_msdc2_apsrc_req_mask_b = 1,
+	.reg_msdc2_vrf18_req_mask_b = 1,
+	.reg_msdc2_ddr_en_mask_b = 1,
+	.reg_pcie_srcclkena_mask_b = 1,
+	.reg_pcie_infra_req_mask_b = 1,
+	.reg_pcie_apsrc_req_mask_b = 1,
+	.reg_pcie_vrf18_req_mask_b = 1,
+	.reg_pcie_ddr_en_mask_b = 1,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	.reg_wakeup_event_mask = 0xEFFFFFFF,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+	/* Auto-gen End */
+};
+
+static void spm_set_power_control(struct pwr_ctrl *pwrctrl)
+{
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	write32(&mtk_spm->spm_ap_standby_con,
+		((pwrctrl->reg_wfi_op & 0x1) << 0) |
+		((pwrctrl->reg_wfi_type & 0x1) << 1) |
+		((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
+		((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
+		((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
+		((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
+		((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
+		((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
+
+	/* SPM_SRC6_MASK */
+	write32(&mtk_spm->spm_src6_mask,
+		((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_dpmaif_ddr_en_mask_b & 0x1) << 4));
+
+	/* SPM_SRC_REQ */
+	write32(&mtk_spm->spm_src_req,
+		((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
+		((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
+		((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
+		((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
+		((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
+		((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+		((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+		((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+		((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+		((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+	/* SPM_SRC_MASK */
+	write32(&mtk_spm->spm_src_mask,
+		((pwrctrl->reg_md_srcclkena_0_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_md_srcclkena2infra_req_0_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_md_apsrc2infra_req_0_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_md_apsrc_req_0_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_md_vrf18_req_0_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_md_ddr_en_0_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_md_srcclkena_1_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_md_srcclkena2infra_req_1_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_md_apsrc2infra_req_1_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_md_apsrc_req_1_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_md_vrf18_req_1_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_md_ddr_en_1_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_conn_ddr_en_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_srcclkeni0_srcclkena_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_srcclkeni0_infra_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_srcclkeni1_srcclkena_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_srcclkeni1_infra_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_srcclkeni2_srcclkena_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_srcclkeni2_infra_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_md32_srcclkena_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_md32_infra_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_md32_apsrc_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_md32_vrf18_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_md32_ddr_en_mask_b & 0x1) << 31));
+
+	/* SPM_SRC2_MASK */
+	write32(&mtk_spm->spm_src2_mask,
+		((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_gce_ddr_en_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_cg_check_ddr_en_mask_b & 0x1) << 31));
+
+	/* SPM_SRC3_MASK */
+	write32(&mtk_spm->spm_src3_mask,
+		((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_sw2spm_int0_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_sw2spm_int1_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_sw2spm_int2_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_sw2spm_int3_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_sc_adsp2spm_wakeup_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_sc_sspm2spm_wakeup_mask_b & 0xf) << 6) |
+		((pwrctrl->reg_sc_scp2spm_wakeup_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_csyspwrreq_mask & 0x1) << 11) |
+		((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_mcupm_ddr_en_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 31));
+
+	/* SPM_SRC4_MASK */
+	write32(&mtk_spm->spm_src4_mask,
+		((pwrctrl->ccif_event_mask_b & 0xffff) << 0) |
+		((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_dramc0_md32_infra_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_dramc0_md32_vrf18_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_dramc1_md32_infra_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_dramc1_md32_vrf18_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_dramc0_md32_wakeup_mask & 0x1) << 26) |
+		((pwrctrl->reg_dramc1_md32_wakeup_mask & 0x1) << 27));
+
+	/* SPM_SRC5_MASK */
+	write32(&mtk_spm->spm_src5_mask,
+		((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
+		((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) |
+		((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_pcie_ddr_en_mask_b & 0x1) << 27));
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	write32(&mtk_spm->spm_wakeup_event_mask,
+		((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	write32(&mtk_spm->spm_wakeup_event_ext_mask,
+		((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
+
+	/* Auto-gen End */
+}
+
+static void spm_register_init(void)
+{
+	u32 reg;
+
+	/* enable register control */
+	write32(&mtk_spm->poweron_config_en, SPM_REGWR_CFG_KEY |
+		BCLK_CG_EN_LSB);
+
+	/* init power control register */
+	write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF);
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+
+	/* reset PCM */
+	write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB |
+		PCM_SW_RESET_LSB);
+	write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+	write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
+		REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
+		REG_MD32_APB_INTERNAL_EN_LSB);
+
+	/* initial SPM CLK control register */
+	write32(&mtk_spm->spm_clk_con, read32(&mtk_spm->spm_clk_con) |
+		REG_SYSCLK1_SRC_MD2_SRCCLKENA);
+
+	/* clean wakeup event raw status */
+	write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF);
+
+	/* clean ISR status */
+	write32(&mtk_spm->spm_irq_mask, ISRM_ALL);
+	write32(&mtk_spm->spm_irq_sta, ISRC_ALL);
+	write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL);
+
+	/* init r7 with POWER_ON_VAL1 */
+	write32(&mtk_spm->pcm_reg_data_ini,
+		read32(&mtk_spm->spm_power_on_val1));
+	write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+
+	/* DDR EN de-bounce length to 5us */
+	write32(&mtk_spm->ddr_en_dbc_con0, DDR_EN_DBC_CON0_DEF);
+	write32(&mtk_spm->ddr_en_dbc_con1, REG_ALL_DDR_EN_DBC_EN_LSB);
+
+	/* Configure ARMPLL Control Mode for MCDI */
+	write32(&mtk_spm->armpll_clk_sel, ARMPLL_CLK_SEL_DEF);
+
+	/* Init for SPM Resource ACK */
+	write32(&mtk_spm->spm_resource_ack_con0, SPM_RESOURCE_ACK_CON0_DEF);
+	write32(&mtk_spm->spm_resource_ack_con1, SPM_RESOURCE_ACK_CON1_DEF);
+	write32(&mtk_spm->spm_resource_ack_con2, SPM_RESOURCE_ACK_CON2_DEF);
+	write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF);
+
+	/* Init VCORE DVFS Status */
+	write32(&mtk_spm->spm_dvfs_misc, (read32(&mtk_spm->spm_dvfs_misc) &
+		~(SPM_DVFS_FORCE_ENABLE_LSB)) | (SPM_DVFSRC_ENABLE_LSB));
+	write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF);
+	write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF);
+
+	write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1);
+	write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT);
+
+	/* apm_hw_s1_state_monitor_pause */
+	reg = read32(&mtk_spm->spm_ack_chk_con_3);
+	reg |= (SPM_ACK_CHK_3_CON_HW_MODE_TRIG | SPM_ACK_CHK_3_CON_CLR_ALL);
+	reg &= ~(SPM_ACK_CHK_3_CON_EN);
+	write32(&mtk_spm->spm_ack_chk_con_3, reg);
+}
+
+static void spm_set_sysclk_settle(void)
+{
+	u32 settle;
+
+	write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE);
+	settle = read32(&mtk_spm->spm_clk_settle);
+}
+
+static void spm_code_swapping(void)
+{
+	u32 mask;
+
+	mask = read32(&mtk_spm->spm_wakeup_event_mask);
+	write32(&mtk_spm->spm_wakeup_event_mask,
+		(mask & ~SPM_WAKEUP_EVENT_MASK_BIT0));
+	write32(&mtk_spm->spm_cpu_wakeup_event, 1);
+	write32(&mtk_spm->spm_cpu_wakeup_event, 0);
+	write32(&mtk_spm->spm_wakeup_event_mask, mask);
+}
+
+static void spm_reset_and_init_pcm(void)
+{
+	bool first_load_fw = true;
+	u32 con1;
+
+	/* check the SPM FW is run or not */
+	if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) &
+	    MD32PCM_CFGREG_SW_RSTN_RUN)
+		first_load_fw = false;
+
+	if (!first_load_fw) {
+		spm_code_swapping();
+		/* Backup PCM r0 -> SPM_POWER_ON_VAL0 before reset PCM`*/
+		write32(&mtk_spm->spm_power_on_val0,
+			read32(&mtk_spm->pcm_reg0_data));
+	}
+
+	/* disable r0 and r7 to control power */
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+
+	/* disable pcm timer after leaving FW */
+	write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
+		(read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB));
+
+	/* reset PCM */
+	write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB |
+		PCM_SW_RESET_LSB);
+	write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+
+	/* init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */
+	con1 = read32(&mtk_spm->pcm_con1) & (RG_PCM_WDT_WAKE_LSB);
+	write32(&mtk_spm->pcm_con1, con1 | SPM_REGWR_CFG_KEY |
+		REG_EVENT_LOCK_EN_LSB | REG_SPM_SRAM_ISOINT_B_LSB |
+		RG_AHBMIF_APBEN_LSB | REG_MD32_APB_INTERNAL_EN_LSB);
+}
+
+static void spm_kick_im_to_fetch(void)
+{
+	uintptr_t ptr;
+	u32 pmem_words;
+	u32 total_words;
+	u32 pmem_start;
+	u32 dmem_start;
+	u32 con0;
+
+	ptr = (uintptr_t) spm_firmware_binary + 0x40000000;
+	pmem_words = spm_firmware.pmem_words;
+	total_words = spm_firmware.total_words;
+	pmem_start = spm_firmware.pmem_start;
+	dmem_start = spm_firmware.dmem_start;
+
+	/* tell IM where is PCM code (use slave mode if code existed) */
+	if (read32(&mtk_spm->md32pcm_dma0_src) != ptr ||
+	    read32(&mtk_spm->md32pcm_dma0_dst) != pmem_start ||
+	    read32(&mtk_spm->md32pcm_dma0_wppt) != pmem_words ||
+	    read32(&mtk_spm->md32pcm_dma0_wpto) != dmem_start ||
+	    read32(&mtk_spm->md32pcm_dma0_count) !=  total_words ||
+	    read32(&mtk_spm->md32pcm_dma0_con) !=  MD32PCM_DMA0_CON_VAL) {
+		write32(&mtk_spm->md32pcm_dma0_src, ptr);
+		write32(&mtk_spm->md32pcm_dma0_dst, pmem_start);
+		write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words);
+		write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start);
+		write32(&mtk_spm->md32pcm_dma0_count, total_words);
+		write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL);
+		write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
+	} else {
+		write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
+			SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB);
+	}
+
+	/* kick IM to fetch (only toggle IM_KICK) */
+	con0 = read32(&mtk_spm->pcm_con0);
+	write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+}
+
+static void spm_init_pcm_register(void)
+{
+	/* init r0 with POWER_ON_VAL0 */
+	write32(&mtk_spm->pcm_reg_data_ini,
+		read32(&mtk_spm->spm_power_on_val0));
+	write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+
+	/* init r7 with POWER_ON_VAL1 */
+	write32(&mtk_spm->pcm_reg_data_ini,
+		read32(&mtk_spm->spm_power_on_val1));
+	write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+}
+
+static void spm_set_wakeup_event(struct pwr_ctrl *pwrctrl)
+{
+	u32 val, mask, isr;
+
+	/* toggle event counter clear */
+	write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
+		SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
+
+	/* toggle for reset SYS TIMER start point */
+	write32(&mtk_spm->sys_timer_con, read32(&mtk_spm->sys_timer_con) |
+		SYS_TIMER_START_EN_LSB);
+
+	if (pwrctrl->timer_val_cust == 0)
+		val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
+	else
+		val = pwrctrl->timer_val_cust;
+
+	write32(&mtk_spm->pcm_timer_val, val);
+
+	/* disable pcm timer */
+	write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
+		(read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB));
+
+	/* unmask AP wakeup source */
+	if (pwrctrl->wake_src_cust == 0)
+		mask = pwrctrl->wake_src;
+	else
+		mask = pwrctrl->wake_src_cust;
+
+	if (pwrctrl->reg_csyspwrreq_mask)
+		mask &= ~SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B;
+
+	write32(&mtk_spm->spm_wakeup_event_mask, ~mask);
+
+	/* unmask SPM ISR (keep TWAM setting) */
+	isr = read32(&mtk_spm->spm_irq_mask);
+	write32(&mtk_spm->spm_irq_mask, isr | ISRM_RET_IRQ_AUX);
+
+	/* toggle event counter clear */
+	write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
+		(read32(&mtk_spm->pcm_con1) & ~SPM_EVENT_COUNTER_CLR_LSB));
+
+	/* toggle for reset SYS TIMER start point */
+	write32(&mtk_spm->sys_timer_con, read32(&mtk_spm->sys_timer_con) &
+		~SYS_TIMER_START_EN_LSB);
+}
+
+static void spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
+{
+	/* set PCM flags and data */
+	if (pwrctrl->pcm_flags_cust_clr != 0)
+		pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
+	if (pwrctrl->pcm_flags_cust_set != 0)
+		pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
+	if (pwrctrl->pcm_flags1_cust_clr != 0)
+		pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
+	if (pwrctrl->pcm_flags1_cust_set != 0)
+		pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
+
+	write32(&mtk_spm->spm_sw_flag_0, pwrctrl->pcm_flags);
+	write32(&mtk_spm->spm_sw_flag_1, pwrctrl->pcm_flags1);
+	write32(&mtk_spm->spm_sw_rsv_7, pwrctrl->pcm_flags);
+	write32(&mtk_spm->spm_sw_rsv_8, pwrctrl->pcm_flags1);
+}
+
+static void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl)
+{
+	u32 con0, rstn;
+
+	/* Waiting for loading SPMFW done*/
+	while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
+		;
+
+	/* Init register to match PCM expectation */
+	write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
+	write32(&mtk_spm->spm_bus_protect2_mask_b,
+		SPM_BUS_PROTECT2_MASK_B_DEF);
+	write32(&mtk_spm->pcm_reg_data_ini, 0);
+
+	spm_set_pcm_flags(pwrctrl);
+
+	/* Kick PCM to run (only toggle PCM_KICK) */
+	con0 = read32(&mtk_spm->pcm_con0);
+	write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+
+	/* Reset md32pcm */
+	rstn = read32(&mtk_spm->md32pcm_cfgreg_sw_rstn);
+	write32(&mtk_spm->md32pcm_cfgreg_sw_rstn,
+		rstn | MD32PCM_CFGREG_SW_RSTN_RESET);
+
+	/* Waiting for SPM init done */
+	udelay(SPM_INIT_DONE_US);
+}
+
+int spm_init(void)
+{
+	struct stopwatch sw;
+
+	stopwatch_init(&sw);
+
+	spm_register_init();
+	spm_set_power_control(&spm_init_ctrl);
+	spm_set_sysclk_settle();
+	spm_reset_and_init_pcm();
+	spm_kick_im_to_fetch();
+	spm_init_pcm_register();
+	spm_set_wakeup_event(&spm_init_ctrl);
+	spm_kick_pcm_to_run(&spm_init_ctrl);
+
+	printk(BIOS_INFO, "SPM: %s done in %ld msecs, %s, spm pc = 0x%x\n",
+	       __func__, stopwatch_duration_msecs(&sw), spm_firmware.version,
+	       read32(&mtk_spm->md32pcm_pc));
+
+	return 0;
+}

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 1:

I thought we're going to replace this by a blob?

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 3:

No rule to make target '3rdparty/blobs/soc/mediatek/mt8192/spm_firmware.bin

@yidi, you have to also upload the changes for 3rdparty/blobs, and then a 'update submodule' commit before landing this.

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 4:
> Patch Set 3:
>
> No rule to make target '3rdparty/blobs/soc/mediatek/mt8192/spm_firmware.bin
>
> @yidi, you have to also upload the changes for 3rdparty/blobs, and then a 'update submodule' commit before landing this.

The blob [e-mail][1] is quite different from the blob@googlesource[2].
And I heard from Roger this patch is still using hex array for some reason.
So I think we can either move this patch to the end of the chain or revise the Makefile.

1:https://review.coreboot.org/plugins/gitiles/blobs/+log/refs/heads/master
2:https://chromium.googlesource.com/chromiumos/third_party/coreboot/blobs/+log...

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG@12 
PS4, Line 12: SPM is able to turn off more power saving for
            : the SoC such as DRAM self-refresh
“turn off more power saving” sounds strange.

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG@16 
PS4, Line 16: TEST=Asurada boots up to shell
It didn’t before? I thought it’s about suspend and resume?

[Yidi Lin (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Roger Lu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#9).

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

mediatek/mt8192: add spmfw loader

To support mt8192 power saving during suspend to RAM, this patch loads
spmfw to support SPM suspend. SPM needs its own firmware to do these
power saving in the right timing under correct conditions.
After linux PM suspends, SPM is able to turn off more power saving for
the SoC such as DRAM self-refresh mode and turning off 26M crystal.

BUG=b:159079649
TEST=Asurada boots up to shell

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/common/mtcmos.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,551 insertions(+), 32 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/9

[Yidi Lin (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Roger Lu, Roger Lu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#13).

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

mediatek/mt8192: add spmfw loader

To support mt8192 power saving during suspend to RAM, this patch loads
spmfw to support SPM suspend. SPM needs its own firmware to do these
power saving in the right timing under correct conditions.
After linux PM suspends, SPM is able to turn off more power saving for
the SoC such as DRAM self-refresh mode and turning off 26M crystal.

BUG=b:159079649
TEST=Asurada boots up to shell

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/common/mtcmos.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,551 insertions(+), 32 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/13

[Nicolas Boichat (Code Review)]

Nicolas Boichat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 15:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 947: 		write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
              : 			SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB);
How does this path work? How do you guarantee that the SPM firmware is loaded again if it changed?

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 951: 	/* kick IM to fetch (only toggle IM_KICK) */
The code below does not seem to match what this comment says.

[Yidi Lin (Code Review)]

Hello build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#16).

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

mediatek/mt8192: add spmfw loader

To support mt8192 power saving during suspend to RAM, this patch loads
spmfw to support SPM suspend. SPM needs its own firmware to do these
power saving in the right timing under correct conditions.
After linux PM suspends, SPM is able to turn off more power saving for
the SoC such as DRAM self-refresh mode and turning off 26M crystal.

BUG=b:159079649
TEST=Asurada boots up to shell

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/common/mtcmos.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,551 insertions(+), 32 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/16

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 16:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 947: 		write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
              : 			SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB);
> How does this path work? How do you guarantee that the SPM firmware is loaded again if it changed?

1. The if statement is for SPM DMA to load spmfw from dram to spm sram.
2. The else statement is for telling spm to use the spmfw in spm sram.
3. I checked below printk log to see if spmfw version and spm pc is what I expect.
https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp...

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 951: 	/* kick IM to fetch (only toggle IM_KICK) */
> The code below does not seem to match what this comment says.

Oh.. yeah. The comment is supposed to be removed.
This code is to enable spm clk to make sure SPM DMA can work.

[Nicolas Boichat (Code Review)]

Nicolas Boichat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 16:

(3 comments)

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 926: 0x40000000
Where does this offset come from?

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 947: 		write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
              : 			SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB);
> The if statement is for SPM DMA to load spmfw from dram to spm sram. […]

2 => So when SPM DMA is used, how is spmfw configured to use spm sram?
3 => spm_firmware.version is just a local variable, agree that checking PC makes sense.

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 1052: 	/* Kick PCM to run (only toggle PCM_KICK) */
This is the exact same code as what is in `spm_kick_im_to_fetch`, intended?

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 16:

(3 comments)

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 926: 0x40000000
> Where does this offset come from?

It's for SPM DMA's need. SPM DMA will deduct 0x40000000 after it receives spmfw address provided by software.

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 947: 		write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
              : 			SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB);
> 2 => So when SPM DMA is used, how is spmfw configured to use spm sram? […]

2=> Oh, it is hardware detail design. Need to consult with SPM designer.

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 1052: 	/* Kick PCM to run (only toggle PCM_KICK) */
> This is the exact same code as what is in `spm_kick_im_to_fetch`, intended?

Yes, intended.

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 16:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 947: 		write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
              : 			SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB);
> 2=> Oh, it is hardware detail design. Need to consult with SPM designer.

Replied by SPM Designer:

There is a define file for SPM core to identify which part of SPM SRAM is used as Program Memory or Data Memory. After the DMA completed moving code to SPM SRAM, SPM core reset will be released and start to run code.

[Nicolas Boichat (Code Review)]

Nicolas Boichat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 16:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 947: 		write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
              : 			SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB);
> Replied by SPM Designer: […]

Ack

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 951: 	/* kick IM to fetch (only toggle IM_KICK) */
> Oh.. yeah. The comment is supposed to be removed. […]

Wait, as part of my experiments, I did print mtk_spm->md32pcm_dma0_rlct _before_ this, and the DMA is already copying content, before the clock is enabled here.

{
    		u32 rlct[32]; int i;
    		for (i = 0; i < ARRAY_SIZE(rlct); i++) {
    			rlct[i] = read32(&mtk_spm->md32pcm_dma0_rlct);
    			/* Waiting for SPM init done */
    			udelay(1);
    		}

printk(BIOS_INFO, "spm md32pcm_dma0_rlct @%08lx\n", (long)&mtk_spm->md32pcm_dma0_rlct);
    		for (i = 0; i < ARRAY_SIZE(rlct); i++)
    			printk(BIOS_INFO, "spm rlct[%d] = 0x%x\n", i, rlct[i]);
    	}

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 16:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 951: 	/* kick IM to fetch (only toggle IM_KICK) */
> Wait, as part of my experiments, I did print mtk_spm->md32pcm_dma0_rlct _before_ this, and the DMA i […]

Oh, it means spm clk has been set on before Line 953 and, in this case, SPM DMA will start after Line 945 is set.

[Nicolas Boichat (Code Review)]

Nicolas Boichat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 16:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 951: 	/* kick IM to fetch (only toggle IM_KICK) */
> Oh, it means spm clk has been set on before Line 953 and, in this case, SPM DMA will start after Lin […]

Right, so that change seems useless (but does not seem to make any difference, nevertheless...)

[Nicolas Boichat (Code Review)]

Nicolas Boichat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 17:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
PS17, Line 931: 
Please consider adding the assertions here:

https://review.coreboot.org/c/coreboot/+/47283/3/src/soc/mediatek/mt8192/spm...

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
PS17, Line 945: 		write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
Is it useful to add this:
write32(&mtk_spm->md32pcm_dma0_start, 0);

just before, just in case (unless the registers don't work this way...)

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 17:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
PS17, Line 931:
> Please consider adding the assertions here: […]

Ok. I'll discuss the SPM designer. Thanks for the advice.

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
PS17, Line 945: 		write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
> Is it useful to add this: […]

Ok. I'll discuss the SPM designer. Thanks for the advice.

[Yidi Lin (Code Review)]

Hello build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#18).

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

mediatek/mt8192: add spmfw loader

To support mt8192 power saving during suspend to RAM, this patch loads
spmfw to support SPM suspend. SPM needs its own firmware to do these
power saving in the right timing under correct conditions.
After linux PM suspends, SPM is able to turn off more power saving for
the SoC such as DRAM self-refresh mode and turning off 26M crystal.

BUG=b:159079649
TEST=Asurada boots up to shell

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/common/mtcmos.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,194 insertions(+), 32 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/18

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 18:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
PS17, Line 931:
> Ok. I'll discuss the SPM designer. Thanks for the advice.

Done

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
PS17, Line 945: 		write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
> Ok. I'll discuss the SPM designer. Thanks for the advice.

Wait SPM designer response.

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 18:

(2 comments)

move last review from CB:47287

https://review.coreboot.org/c/coreboot/+/46389/18/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/18/src/soc/mediatek/mt8192/sp... 
PS18, Line 12: #define SPMFW_HEADER_SIZE	(16)
Yu-Ping Wu
Nov 11
No need for the parentheses.

https://review.coreboot.org/c/coreboot/+/46389/18/src/soc/mediatek/mt8192/sp... 
PS18, Line 583: offset += SPMFW_HEADER_SIZE; /* binary start offset */
Yu-Ping Wu
Nov 11
If this number is a constant, should we write

offset = SPMFW_HEADER_SIZE
instead?

[Yidi Lin (Code Review)]

Hello build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#22).

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

mediatek/mt8192: add spmfw loader

To support mt8192 power saving during suspend to RAM, this patch loads
spmfw to support SPM suspend. SPM needs its own firmware to do these
power saving in the right timing under correct conditions.
After linux PM suspends, SPM is able to turn off more power saving for
the SoC such as DRAM self-refresh mode and turning off 26M crystal.

BUG=b:159079649
TEST=Asurada boots up to shell

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/common/mtcmos.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,194 insertions(+), 32 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/22

[Yidi Lin (Code Review)]

Hello build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#23).

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

mediatek/mt8192: add spmfw loader

To support mt8192 power saving during suspend to RAM, this patch loads
spmfw to support SPM suspend. SPM needs its own firmware to do these
power saving in the right timing under correct conditions.
After linux PM suspends, SPM is able to turn off more power saving for
the SoC such as DRAM self-refresh mode and turning off 26M crystal.

BUG=b:159079649
TEST=Asurada boots up to shell

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/common/mtcmos.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,197 insertions(+), 32 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/23

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 24:

(5 comments)

We still have one comment that needs SPM DE's reply.

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 926: 0x40000000
> It's for SPM DMA's need. […]

Ack

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 951: 	/* kick IM to fetch (only toggle IM_KICK) */
> Right, so that change seems useless (but does not seem to make any difference, nevertheless... […]

Ack

https://review.coreboot.org/c/coreboot/+/46389/15/src/soc/mediatek/mt8192/sp... 
PS15, Line 1052: 	/* Kick PCM to run (only toggle PCM_KICK) */
> Yes, intended.

Ack

https://review.coreboot.org/c/coreboot/+/46389/18/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/18/src/soc/mediatek/mt8192/sp... 
PS18, Line 12: #define SPMFW_HEADER_SIZE	(16)
> Yu-Ping Wu […]

Done

https://review.coreboot.org/c/coreboot/+/46389/18/src/soc/mediatek/mt8192/sp... 
PS18, Line 583: offset += SPMFW_HEADER_SIZE; /* binary start offset */
> Yu-Ping Wu […]

Done

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 25:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/25/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/25/src/soc/mediatek/mt8192/sp... 
PS25, Line 21: 	.reg_wfi_op = 0,
             : 	.reg_wfi_type = 0,
             : 	.reg_mp0_cputop_idle_mask = 0,
             : 	.reg_mp1_cputop_idle_mask = 0,
             : 	.reg_mcusys_idle_mask = 0,
             : 	.reg_md_apsrc_1_sel = 0,
             : 	.reg_md_apsrc_0_sel = 0,
             : 	.reg_conn_apsrc_sel = 0,
             : 
static variable is always 0, so please remove the =0 fields.

https://review.coreboot.org/c/coreboot/+/46389/25/src/soc/mediatek/mt8192/sp... 
PS25, Line 438: settle
never used?

[Yidi Lin (Code Review)]

Hello build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#26).

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

mediatek/mt8192: add spmfw loader

To support mt8192 power saving during suspend to RAM, this patch loads
spmfw to support SPM suspend. SPM needs its own firmware to do these
power saving in the right timing under correct conditions.
After linux PM suspends, SPM is able to turn off more power saving for
the SoC such as DRAM self-refresh mode and turning off 26M crystal.

BUG=b:159079649
TEST=Asurada boots up to shell

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/common/mtcmos.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,137 insertions(+), 32 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/26

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 26:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/25/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/25/src/soc/mediatek/mt8192/sp... 
PS25, Line 21: 	.reg_wfi_op = 0,
             : 	.reg_wfi_type = 0,
             : 	.reg_mp0_cputop_idle_mask = 0,
             : 	.reg_mp1_cputop_idle_mask = 0,
             : 	.reg_mcusys_idle_mask = 0,
             : 	.reg_md_apsrc_1_sel = 0,
             : 	.reg_md_apsrc_0_sel = 0,
             : 	.reg_conn_apsrc_sel = 0,
             :
> static variable is always 0, so please remove the =0 fields.

Done

https://review.coreboot.org/c/coreboot/+/46389/25/src/soc/mediatek/mt8192/sp... 
PS25, Line 438: settle
> never used?

Done

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 26:

(33 comments)

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/common/mt... 
File src/soc/mediatek/common/mtcmos.c:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/common/mt... 
PS26, Line 26: poweron_config_en
MT8183 uses poweron_config_set, while MT8192 has poweron_config_en, so we can't simply change it like this. I'd suggest having consistent naming.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/Ma... 
File src/soc/mediatek/mt8192/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/Ma... 
PS26, Line 42: ramstage-y += spm.c
Put this after soc.c?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/in... 
File src/soc/mediatek/mt8192/include/soc/spm.h:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/in... 
PS26, Line 11: (
No need for parentheses.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/in... 
PS26, Line 59: (
No need for parentheses for a single number. Same below.

For "(30 * 32768)" however, we need to keep the parentheses.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/in... 
PS26, Line 90: (
Same.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/in... 
PS26, Line 109: (
Same.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/in... 
PS26, Line 639: 0
Be consistent and remove the leading zeros?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 314: SPM_REGWR_CFG_KEY
Move this to the next line for readability.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 322: SPM_REGWR_CFG_KEY
Same.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 325: SPM_REGWR_CFG_KEY
Same.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 330: write32(&mtk_spm->spm_clk_con, read32(&mtk_spm->spm_clk_con) |
              : 		REG_SYSCLK1_SRC_MD2_SRCCLKENA);
Can we use clrsetbits32 or SET32_BITFIELDS?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 361: write32(&mtk_spm->spm_dvfs_misc, (read32(&mtk_spm->spm_dvfs_misc) &
              : 		~(SPM_DVFS_FORCE_ENABLE_LSB)) | (SPM_DVFSRC_ENABLE_LSB));
Can we use clrsetbits32 or SET32_BITFIELDS?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 370: reg = read32(&mtk_spm->spm_ack_chk_con_3);
              : 	reg |= (SPM_ACK_CHK_3_CON_HW_MODE_TRIG | SPM_ACK_CHK_3_CON_CLR_ALL);
              : 	reg &= ~(SPM_ACK_CHK_3_CON_EN);
              : 	write32(&mtk_spm->spm_ack_chk_con_3, reg);
Can we use clrsetbits32 or SET32_BITFIELDS?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 387: (
No need for parentheses.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 414: write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
              : 		(read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB));
Use SET32_BITFIELDS?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 418: SPM_REGWR_CFG_KEY
Move to next line.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 420: SPM_REGWR_CFG_KEY
Same.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 423: (
No need for parentheses.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 424: con1
Same.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 450: (
No need for parentheses. Same below.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 455: t
T

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 460:   
Remove one space.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 461:   
Remove one space.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 470: write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
              : 			SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB);
Use SET32_BITFIELDS?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 474: k
K

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 551: write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
              : 		SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
Use SET32_BITFIELDS?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 555: write32(&mtk_spm->sys_timer_con, read32(&mtk_spm->sys_timer_con) |
              : 		SYS_TIMER_START_EN_LSB);
Use SET32_BITFIELDS?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 566: write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
              : 		(read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB));
Use SET32_BITFIELDS?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 581: isr = read32(&mtk_spm->spm_irq_mask);
              : 	write32(&mtk_spm->spm_irq_mask, isr | ISRM_RET_IRQ_AUX);
Use SET32_BITFIELDS?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 585: write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
              : 		(read32(&mtk_spm->pcm_con1) & ~SPM_EVENT_COUNTER_CLR_LSB));
Use SET32_BITFIELDS?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 589: write32(&mtk_spm->sys_timer_con, read32(&mtk_spm->sys_timer_con) &
              : 		~SYS_TIMER_START_EN_LSB);
Use SET32_BITFIELDS?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 628: con0 = read32(&mtk_spm->pcm_con0);
              : 	write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
Use SET32_BITFIELDS?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 632: rstn = read32(&mtk_spm->md32pcm_cfgreg_sw_rstn);
              : 	write32(&mtk_spm->md32pcm_cfgreg_sw_rstn,
              : 		rstn | MD32PCM_CFGREG_SW_RSTN_RESET);
Use SET32_BITFIELDS?

[Yidi Lin (Code Review)]

Hello build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#27).

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

mediatek/mt8192: add spmfw loader

To support mt8192 power saving during suspend to RAM, this patch loads
spmfw to support SPM suspend. SPM needs its own firmware to do these
power saving in the right timing under correct conditions.
After linux PM suspends, SPM is able to turn off more power saving for
the SoC such as DRAM self-refresh mode and turning off 26M crystal.

BUG=b:159079649
TEST=Asurada boots up to shell

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
4 files changed, 1,128 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/27

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 28:

(32 comments)

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/common/mt... 
File src/soc/mediatek/common/mtcmos.c:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/common/mt... 
PS26, Line 26: poweron_config_en
> MT8183 uses poweron_config_set, while MT8192 has poweron_config_en, so we can't simply change it lik […]

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/Ma... 
File src/soc/mediatek/mt8192/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/Ma... 
PS26, Line 42: ramstage-y += spm.c
> Put this after soc. […]

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/in... 
File src/soc/mediatek/mt8192/include/soc/spm.h:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/in... 
PS26, Line 11: (
> No need for parentheses.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/in... 
PS26, Line 59: (
> No need for parentheses for a single number. Same below. […]

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/in... 
PS26, Line 90: (
> Same.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/in... 
PS26, Line 109: (
> Same.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/in... 
PS26, Line 639: 0
> Be consistent and remove the leading zeros?

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 314: SPM_REGWR_CFG_KEY
> Move this to the next line for readability.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 322: SPM_REGWR_CFG_KEY
> Same.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 325: SPM_REGWR_CFG_KEY
> Same.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 330: write32(&mtk_spm->spm_clk_con, read32(&mtk_spm->spm_clk_con) |
              : 		REG_SYSCLK1_SRC_MD2_SRCCLKENA);
> Can we use clrsetbits32 or SET32_BITFIELDS?

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 361: write32(&mtk_spm->spm_dvfs_misc, (read32(&mtk_spm->spm_dvfs_misc) &
              : 		~(SPM_DVFS_FORCE_ENABLE_LSB)) | (SPM_DVFSRC_ENABLE_LSB));
> Can we use clrsetbits32 or SET32_BITFIELDS?

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 370: reg = read32(&mtk_spm->spm_ack_chk_con_3);
              : 	reg |= (SPM_ACK_CHK_3_CON_HW_MODE_TRIG | SPM_ACK_CHK_3_CON_CLR_ALL);
              : 	reg &= ~(SPM_ACK_CHK_3_CON_EN);
              : 	write32(&mtk_spm->spm_ack_chk_con_3, reg);
> Can we use clrsetbits32 or SET32_BITFIELDS?

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 387: (
> No need for parentheses.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 414: write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
              : 		(read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB));
> Use SET32_BITFIELDS?

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 418: SPM_REGWR_CFG_KEY
> Move to next line.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 420: SPM_REGWR_CFG_KEY
> Same.

No exceed 80 lines. Therefore, Keep the same line.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 423: (
> No need for parentheses.

miss this one, will fix in the next patch.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 424: con1
> Same.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 450: (
> No need for parentheses. Same below.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 455: t
> T

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 460:
> Remove one space.

miss this one, will fix in the next patch.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 461:
> Remove one space.

miss this one, will fix in the next patch.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 470: write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
              : 			SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB);
> Use SET32_BITFIELDS?

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 474: k
> K

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 551: write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) |
              : 		SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
> Use SET32_BITFIELDS?

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 555: write32(&mtk_spm->sys_timer_con, read32(&mtk_spm->sys_timer_con) |
              : 		SYS_TIMER_START_EN_LSB);
> Use SET32_BITFIELDS?

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 581: isr = read32(&mtk_spm->spm_irq_mask);
              : 	write32(&mtk_spm->spm_irq_mask, isr | ISRM_RET_IRQ_AUX);
> Use SET32_BITFIELDS?

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 585: write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
              : 		(read32(&mtk_spm->pcm_con1) & ~SPM_EVENT_COUNTER_CLR_LSB));
> Use SET32_BITFIELDS?

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 589: write32(&mtk_spm->sys_timer_con, read32(&mtk_spm->sys_timer_con) &
              : 		~SYS_TIMER_START_EN_LSB);
> Use SET32_BITFIELDS?

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 628: con0 = read32(&mtk_spm->pcm_con0);
              : 	write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
> Use SET32_BITFIELDS?

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 632: rstn = read32(&mtk_spm->md32pcm_cfgreg_sw_rstn);
              : 	write32(&mtk_spm->md32pcm_cfgreg_sw_rstn,
              : 		rstn | MD32PCM_CFGREG_SW_RSTN_RESET);
> Use SET32_BITFIELDS?

Done

[Yidi Lin (Code Review)]

Hello build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#29).

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

mediatek/mt8192: add spmfw loader

To support mt8192 power saving during suspend to RAM, this patch loads
spmfw to support SPM suspend. SPM needs its own firmware to do these
power saving in the right timing under correct conditions.
After linux PM suspends, SPM is able to turn off more power saving for
the SoC such as DRAM self-refresh mode and turning off 26M crystal.

BUG=b:159079649
TEST=Asurada boots up to shell

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
4 files changed, 1,128 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/29

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 29:

(3 comments)

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 423: (
> miss this one, will fix in the next patch.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 460:
> miss this one, will fix in the next patch.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 461:
> miss this one, will fix in the next patch.

Done

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 29:

(3 comments)

There're still unresolved comments in PS4 and PS17.

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
PS17, Line 945: 		write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
> Wait SPM designer response.

Update?

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 566: write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
              : 		(read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB));
> Use SET32_BITFIELDS?

Forgot this?

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
PS29, Line 421: con1 = read32(&mtk_spm->pcm_con1) & RG_PCM_WDT_WAKE_LSB;
              : 	write32(&mtk_spm->pcm_con1,
              : 		con1 | SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
              : 		REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
              : 		REG_MD32_APB_INTERNAL_EN_LSB);
Use clrsetbits32?

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 29:

(3 comments)

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
PS17, Line 945: 		write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
> Update?

write32(&mtk_spm->md32pcm_dma0_start, 0); => It is not necessary and can be removed.

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 566: write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
              : 		(read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB));
> Forgot this?

It is fixed in https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp....

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
PS29, Line 421: con1 = read32(&mtk_spm->pcm_con1) & RG_PCM_WDT_WAKE_LSB;
              : 	write32(&mtk_spm->pcm_con1,
              : 		con1 | SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
              : 		REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
              : 		REG_MD32_APB_INTERNAL_EN_LSB);
> Use clrsetbits32?

The original code keeps PCM WDT setting from con1 only and assign new bits to con1 register. So, it cannot be replaced with clrsetbits32.

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 29:

(3 comments)

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/17/src/soc/mediatek/mt8192/sp... 
PS17, Line 945: 		write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
> write32(&mtk_spm->md32pcm_dma0_start, 0); => It is not necessary and can be removed.

Done

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 566: write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
              : 		(read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB));
> It is fixed in https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp....

Done

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
PS29, Line 421: con1 = read32(&mtk_spm->pcm_con1) & RG_PCM_WDT_WAKE_LSB;
              : 	write32(&mtk_spm->pcm_con1,
              : 		con1 | SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
              : 		REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
              : 		REG_MD32_APB_INTERNAL_EN_LSB);
> The original code keeps PCM WDT setting from con1 only and assign new bits to con1 register. […]

Ack

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 29:

(1 comment)

There're still unresolved comments in PS4

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
PS29, Line 421: con1 = read32(&mtk_spm->pcm_con1) & RG_PCM_WDT_WAKE_LSB;
              : 	write32(&mtk_spm->pcm_con1,
              : 		con1 | SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
              : 		REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
              : 		REG_MD32_APB_INTERNAL_EN_LSB);
> The original code keeps PCM WDT setting from con1 only and assign new bits to con1 register. […]

Isn't this equivalent to the following?

clrsetbits32(&mtk_spm->pcm_con1, ~RG_PCM_WDT_WAKE_LSB,
    	SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
    	REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
    	REG_MD32_APB_INTERNAL_EN_LSB);

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 29:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/26/src/soc/mediatek/mt8192/sp... 
PS26, Line 566: write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY |
              : 		(read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB));
> Forgot this?

Done

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
PS29, Line 421: con1 = read32(&mtk_spm->pcm_con1) & RG_PCM_WDT_WAKE_LSB;
              : 	write32(&mtk_spm->pcm_con1,
              : 		con1 | SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
              : 		REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
              : 		REG_MD32_APB_INTERNAL_EN_LSB);
> Isn't this equivalent to the following? […]

Hi Yu-Ping,
con1 value could be 0 or (1U << 9).

Roger,
Please consult with DE if bit 9 of pcm_con1 could be always set to 0 or 1 at boot time.

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 29:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG@12 
PS4, Line 12: SPM is able to turn off more power saving for
            : the SoC such as DRAM self-refresh
> “turn off more power saving” sounds strange.

Hi Paul, is this ok?

This patch helps load spmfw from cbfs to spm sram. Spm needs its own firmware to enable spm suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend.

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG@16 
PS4, Line 16: TEST=Asurada boots up to shell
> It didn’t before? I thought it’s about suspend and resume?

Hi Paul, Yes. It's about system suspend/resume and I will the change TEST comment as below.

TEST=Asurada system suspend/resume ok

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 29:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
PS29, Line 421: con1 = read32(&mtk_spm->pcm_con1) & RG_PCM_WDT_WAKE_LSB;
              : 	write32(&mtk_spm->pcm_con1,
              : 		con1 | SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
              : 		REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
              : 		REG_MD32_APB_INTERNAL_EN_LSB);
> Hi Yu-Ping, […]

clrsetbits32(addr, clear, set) will be expanded to

write32((read32(addr) & ~clear) | set)

so clrsetbits32(addr, ~RG_PCM_WDT_WAKE_LSB, set) will be expanded to

write32((read32(addr) & RG_PCM_WDT_WAKE_LSB) | set)

which is *exactly* the same as what is written now. Am I misunderstanding anything?

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 29:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG@12 
PS4, Line 12: SPM is able to turn off more power saving for
            : the SoC such as DRAM self-refresh
> Hi Paul, is this ok? […]

Please go ahead and change it. Reviewers will leave another comment if needed.

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG@16 
PS4, Line 16: TEST=Asurada boots up to shell
> I will the change TEST comment as below.

Instead of saying something WILL be done, please *first* upload a new patchset to fix this, and *then* resolve the comment saying it's done.

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 29:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
PS29, Line 421: con1 = read32(&mtk_spm->pcm_con1) & RG_PCM_WDT_WAKE_LSB;
              : 	write32(&mtk_spm->pcm_con1,
              : 		con1 | SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
              : 		REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
              : 		REG_MD32_APB_INTERNAL_EN_LSB);
> Hi Yu-Ping, […]

Hi Yu-Ping, you are right. I'll change it to clrsetbits32 in the next patch. Thanks for the reminding.

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 29:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/29/src/soc/mediatek/mt8192/sp... 
PS29, Line 421: con1 = read32(&mtk_spm->pcm_con1) & RG_PCM_WDT_WAKE_LSB;
              : 	write32(&mtk_spm->pcm_con1,
              : 		con1 | SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
              : 		REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
              : 		REG_MD32_APB_INTERNAL_EN_LSB);
> clrsetbits32(addr, clear, set) will be expanded to […]

My fault, I miss "~"RG_PCM_WDT_WAKE_LSB.

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 29:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG@12 
PS4, Line 12: SPM is able to turn off more power saving for
            : the SoC such as DRAM self-refresh
> Please go ahead and change it. Reviewers will leave another comment if needed.

Ok. Thanks.

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG@16 
PS4, Line 16: TEST=Asurada boots up to shell
> > I will the change TEST comment as below. […]

Ok. Thanks.

[Yidi Lin (Code Review)]

Hello build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#30).

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

mediatek/mt8192: add spmfw loader

This patch helps load spmfw from cbfs to spm sram. Spm needs its own
firmware to enable spm suspend/resume function which turns off several
resources such as DRAM/mainpll/26M clk when linux system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
4 files changed, 1,126 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/30

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 30:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG@12 
PS4, Line 12: SPM is able to turn off more power saving for
            : the SoC such as DRAM self-refresh
> Ok. Thanks.

Done

https://review.coreboot.org/c/coreboot/+/46389/4//COMMIT_MSG@16 
PS4, Line 16: TEST=Asurada boots up to shell
> Ok. Thanks.

Done

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 30:

(2 comments)

Final 2 nits!

https://review.coreboot.org/c/coreboot/+/46389/30//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46389/30//COMMIT_MSG@7 
PS30, Line 7: mediatek
soc/mediatek

https://review.coreboot.org/c/coreboot/+/46389/30//COMMIT_MSG@9 
PS30, Line 9: helps load spmfw
adds support for loading spm firmware

[Nicolas Boichat (Code Review)]

Nicolas Boichat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 30:

(4 comments)

A few more comments, since I fought with that code for a bit ,-)

https://review.coreboot.org/c/coreboot/+/46389/18/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/18/src/soc/mediatek/mt8192/sp... 
PS18, Line 599: 
Do you also want to check that firmware_size == pcm->desc.total_words?

(old comment that I forgot to submit)

https://review.coreboot.org/c/coreboot/+/46389/30/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/30/src/soc/mediatek/mt8192/sp... 
PS30, Line 14: static struct pwr_ctrl spm_init_ctrl = {
do you want to add a const here, so that the compiler can hopefully optimize some of the code below?

(we should probably look at the generated assembly to confirm: the functions below can shrink to very little code if the compiler is able to figure that out)

https://review.coreboot.org/c/coreboot/+/46389/30/src/soc/mediatek/mt8192/sp... 
PS30, Line 471: 	/* Kick IM to fetch (only toggle IM_KICK) */
I think I commented on an earlier version, this comment does not seem to match the code? (kick sounds a bit different than clock enable)

https://review.coreboot.org/c/coreboot/+/46389/30/src/soc/mediatek/mt8192/sp... 
PS30, Line 472: 	con0 = read32(&mtk_spm->pcm_con0);
              : 	write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);

[Yidi Lin (Code Review)]

Hello build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#31).

Change subject: mediatek/mt8192: add spmfw loader
......................................................................

mediatek/mt8192: add spmfw loader

This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
4 files changed, 1,128 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/31

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Roger Lu (Code Review)]

Roger Lu has uploaded a new patch set (#32) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

soc/mediatek/mt8192: add spmfw loader

This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
4 files changed, 1,128 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/32

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Nicolas Boichat (Code Review)]

Nicolas Boichat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 32: Code-Review+1

(3 comments)

Thanks!

https://review.coreboot.org/c/coreboot/+/46389/30/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/30/src/soc/mediatek/mt8192/sp... 
PS30, Line 14: static struct pwr_ctrl spm_init_ctrl = {
> do you want to add a const here, so that the compiler can hopefully optimize some of the code below? […]

Done

https://review.coreboot.org/c/coreboot/+/46389/30/src/soc/mediatek/mt8192/sp... 
PS30, Line 471: 	/* Kick IM to fetch (only toggle IM_KICK) */
> I think I commented on an earlier version, this comment does not seem to match the code? (kick sound […]

Done

https://review.coreboot.org/c/coreboot/+/46389/30/src/soc/mediatek/mt8192/sp... 
PS30, Line 472: 	con0 = read32(&mtk_spm->pcm_con0);
              : 	write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
> setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);

Done

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Hello Hung-Te Lin, build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu, Nicolas Boichat,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#33).

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

soc/mediatek/mt8192: add spmfw loader

This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
4 files changed, 1,128 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/33

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 33:

(3 comments)

https://review.coreboot.org/c/coreboot/+/46389/30//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46389/30//COMMIT_MSG@7 
PS30, Line 7: mediatek
> soc/mediatek

Done

https://review.coreboot.org/c/coreboot/+/46389/30//COMMIT_MSG@9 
PS30, Line 9: helps load spmfw
> adds support for loading spm firmware

Done

https://review.coreboot.org/c/coreboot/+/46389/18/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/18/src/soc/mediatek/mt8192/sp... 
PS18, Line 599:
> Do you also want to check that firmware_size == pcm->desc.total_words? […]

Done

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 33:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/33/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/33/src/soc/mediatek/mt8192/sp... 
PS33, Line 498: cbfs_boot_load_file
I think we can still use mtlib_load_and_run, just move the parsing code (below) to the reset_mcu callback.

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 33:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/33/src/soc/mediatek/mt8192/Ma... 
File src/soc/mediatek/mt8192/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/46389/33/src/soc/mediatek/mt8192/Ma... 
PS33, Line 53: cbfs-files-y += spm_firmware.bin
             : spm_firmware.bin-file := $(MT8192_BLOB_DIR)/spm_firmware.bin
             : spm_firmware.bin-type := raw
             : spm_firmware.bin-compression := $(CBFS_COMPRESS_FLAG)
If we will be adding a lot of firmware files like this, I think we should:

1. Define the blob name in Kconfig, say CONFIG_SPM_FIRMWARE = "spm_firmware.bin"
2. In *.c use CONFIG_SPM_FIRMWARE instead of putting another name there
3. Add a rule in Makefile.inc so we can easily add them, say

mcu-firmware-files += $(CONFIG_SPM_FIRMARE)

$(foreach fw, $(mcu-firmware-files), ...
    $(eval $(fw)-file := $(MT8192_BLOB_DIR)/$(fw))
    ...
 )

Also we can add 'ifneq ($(wildcard ...))' so we won't see build failure even if the blobs don't exist.

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 33:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/33/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/33/src/soc/mediatek/mt8192/sp... 
PS33, Line 498: cbfs_boot_load_file
> I think we can still use mtlib_load_and_run, just move the parsing code (below) to the reset_mcu cal […]

The parsing code requires file_size for checking offset.
So we need to pass file_size to reset_mcu callback.

Could you also review CB:47896 ?

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Hello Hung-Te Lin, build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu, Nicolas Boichat,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#34).

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

soc/mediatek/mt8192: add spmfw loader

This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,138 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/34

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 34:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/33/src/soc/mediatek/mt8192/Ma... 
File src/soc/mediatek/mt8192/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/46389/33/src/soc/mediatek/mt8192/Ma... 
PS33, Line 53: cbfs-files-y += spm_firmware.bin
             : spm_firmware.bin-file := $(MT8192_BLOB_DIR)/spm_firmware.bin
             : spm_firmware.bin-type := raw
             : spm_firmware.bin-compression := $(CBFS_COMPRESS_FLAG)
> If we will be adding a lot of firmware files like this, I think we should: […]

Done

https://review.coreboot.org/c/coreboot/+/46389/33/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/33/src/soc/mediatek/mt8192/sp... 
PS33, Line 498: cbfs_boot_load_file
> The parsing code requires file_size for checking offset. […]

Ack

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 34:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/33/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/33/src/soc/mediatek/mt8192/sp... 
PS33, Line 498: cbfs_boot_load_file
> Ack

I think CB:47896 looks pretty good, can we merge that WIP to these changes?

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Hello Hung-Te Lin, build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu, Nicolas Boichat,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#35).

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

soc/mediatek/mt8192: add spmfw loader

This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,143 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/35

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Hello Hung-Te Lin, build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu, Nicolas Boichat,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#36).

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

soc/mediatek/mt8192: add spmfw loader

This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,143 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/36

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 36:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/Kc... 
File src/soc/mediatek/mt8192/Kconfig:

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/Kc... 
PS35, Line 49: "The file name of the MediaTek SPM firmware"
You don't need to add this (unless if you want to allow developers overriding that when 'make menu'; but I'd say that's usually a bad idea - this should be changed in Kconfig files.

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 36:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/36/src/soc/mediatek/mt8192/Ma... 
File src/soc/mediatek/mt8192/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/46389/36/src/soc/mediatek/mt8192/Ma... 
PS36, Line 53: mcu-firmware-files := $(CONFIG_SPM_FIRMWARE)
let's make this multiline:

mcu-firmware-files := \
         $(CONFIG_SPM_FIRMWARE)

So it's easier to add more in future.

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 36:

(3 comments)

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
PS35, Line 436: 0x40000000
please use DRAM_START instead of hard-coded values.
(or another name so it's easier to figure out what this value means, especially if we change DRAM_START address someday)

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
PS35, Line 443: BIOS_INFO
more like DEBUG?

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
PS35, Line 453: if (read32(&mtk_spm->md32pcm_dma0_src) != ptr ||
              : 	    read32(&mtk_spm->md32pcm_dma0_dst) != pmem_start ||
              : 	    read32(&mtk_spm->md32pcm_dma0_wppt) != pmem_words ||
              : 	    read32(&mtk_spm->md32pcm_dma0_wpto) != dmem_start ||
              : 	    read32(&mtk_spm->md32pcm_dma0_count) != total_words ||
              : 	    read32(&mtk_spm->md32pcm_dma0_con) != MD32PCM_DMA0_CON_VAL) {
why do we need to do slave mode if the regs look correct?
how can we be sure if the IM has correct data, since there's no checksum?

what about we simply always kick IM to re-fetch?

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 36:

(3 comments)

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
PS35, Line 436: 0x40000000
> please use DRAM_START instead of hard-coded values. […]

Ok. I'll name it in the next patch.

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
PS35, Line 443: BIOS_INFO
> more like DEBUG?

Ok. I'll change it to DEBUG.

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
PS35, Line 453: if (read32(&mtk_spm->md32pcm_dma0_src) != ptr ||
              : 	    read32(&mtk_spm->md32pcm_dma0_dst) != pmem_start ||
              : 	    read32(&mtk_spm->md32pcm_dma0_wppt) != pmem_words ||
              : 	    read32(&mtk_spm->md32pcm_dma0_wpto) != dmem_start ||
              : 	    read32(&mtk_spm->md32pcm_dma0_count) != total_words ||
              : 	    read32(&mtk_spm->md32pcm_dma0_con) != MD32PCM_DMA0_CON_VAL) {
> why do we need to do slave mode if the regs look correct? […]

1. Slave mode won't be used in Chromebook. I save it for completing the mode selection.
2. Currently, we can't.
3. We can read spm_firmware from spm sram back and compare it with the spm_firmware in dram for making sure data consistency. Do we need to do it? Thanks.

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 36:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
PS35, Line 453: if (read32(&mtk_spm->md32pcm_dma0_src) != ptr ||
              : 	    read32(&mtk_spm->md32pcm_dma0_dst) != pmem_start ||
              : 	    read32(&mtk_spm->md32pcm_dma0_wppt) != pmem_words ||
              : 	    read32(&mtk_spm->md32pcm_dma0_wpto) != dmem_start ||
              : 	    read32(&mtk_spm->md32pcm_dma0_count) != total_words ||
              : 	    read32(&mtk_spm->md32pcm_dma0_con) != MD32PCM_DMA0_CON_VAL) {
> Slave mode won't be used in Chromebook. I save it for completing the mode selection. […]

If compared to "checking consistency", I'd rather always kick IM to refetch our trusted data.

Otherwise, I can imaging an exploit like

-> boot into developer mode
 -> load a new malicious SPM firmware 
 -> reboot to normal (secure mode)
 -> firmware sees SPM regs already in good shape and didn't reload
 -> running malicious SPM in normal mode

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Roger Lu (Code Review)]

Roger Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 36:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
PS35, Line 453: if (read32(&mtk_spm->md32pcm_dma0_src) != ptr ||
              : 	    read32(&mtk_spm->md32pcm_dma0_dst) != pmem_start ||
              : 	    read32(&mtk_spm->md32pcm_dma0_wppt) != pmem_words ||
              : 	    read32(&mtk_spm->md32pcm_dma0_wpto) != dmem_start ||
              : 	    read32(&mtk_spm->md32pcm_dma0_count) != total_words ||
              : 	    read32(&mtk_spm->md32pcm_dma0_con) != MD32PCM_DMA0_CON_VAL) {
> If compared to "checking consistency", I'd rather always kick IM to refetch our trusted data. […]

Okay, I see. Let's do "always kick IM to refetch". I'll update it in the next patch.

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 36:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/36/src/soc/mediatek/mt8192/Ma... 
File src/soc/mediatek/mt8192/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/46389/36/src/soc/mediatek/mt8192/Ma... 
PS36, Line 53: mcu-firmware-files := $(CONFIG_SPM_FIRMWARE)
> let's make this multiline: […]

Hi Hung-Te,

Which style do you prefer ?

mcu-firmware-files := \
        $(CONFIG_MCUPM_FIRMWARE) $(CONFIG_SPM_FIRMWARE)
or 
mcu-firmware-files := \
        $(CONFIG_MCUPM_FIRMWARE) \
        $(CONFIG_SPM_FIRMWARE)

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 36:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/36/src/soc/mediatek/mt8192/Ma... 
File src/soc/mediatek/mt8192/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/46389/36/src/soc/mediatek/mt8192/Ma... 
PS36, Line 53: mcu-firmware-files := $(CONFIG_SPM_FIRMWARE)
> Hi Hung-Te, […]

The later

mcu-firmware-files := \
        $(CONFIG_MCUPM_FIRMWARE) \
        $(CONFIG_SPM_FIRMWARE)

(if you merge the two files in one line then there's no advantage)

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Hello Hung-Te Lin, build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu, Nicolas Boichat,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#37).

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

soc/mediatek/mt8192: add spmfw loader

This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,134 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/37

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 37:

(5 comments)

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/Kc... 
File src/soc/mediatek/mt8192/Kconfig:

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/Kc... 
PS35, Line 49: "The file name of the MediaTek SPM firmware"
> You don't need to add this (unless if you want to allow developers overriding that when 'make menu'; […]

Done

https://review.coreboot.org/c/coreboot/+/46389/36/src/soc/mediatek/mt8192/Ma... 
File src/soc/mediatek/mt8192/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/46389/36/src/soc/mediatek/mt8192/Ma... 
PS36, Line 53: mcu-firmware-files := $(CONFIG_SPM_FIRMWARE)
> The later […]

Done

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
PS35, Line 436: 0x40000000
> Ok. I'll name it in the next patch.

Done

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
PS35, Line 443: BIOS_INFO
> Ok. I'll change it to DEBUG.

Done

https://review.coreboot.org/c/coreboot/+/46389/35/src/soc/mediatek/mt8192/sp... 
PS35, Line 453: if (read32(&mtk_spm->md32pcm_dma0_src) != ptr ||
              : 	    read32(&mtk_spm->md32pcm_dma0_dst) != pmem_start ||
              : 	    read32(&mtk_spm->md32pcm_dma0_wppt) != pmem_words ||
              : 	    read32(&mtk_spm->md32pcm_dma0_wpto) != dmem_start ||
              : 	    read32(&mtk_spm->md32pcm_dma0_count) != total_words ||
              : 	    read32(&mtk_spm->md32pcm_dma0_con) != MD32PCM_DMA0_CON_VAL) {
> Okay, I see. Let's do "always kick IM to refetch". I'll update it in the next patch.

Done

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 37: Code-Review+1

(1 comment)

just some nits

https://review.coreboot.org/c/coreboot/+/46389/37/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/37/src/soc/mediatek/mt8192/sp... 
PS37, Line 645: %s() failed
SPM: %s: failed in mtlib_init_mcu.\n", __func__

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 37:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46389/37/src/soc/mediatek/mt8192/Ma... 
File src/soc/mediatek/mt8192/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/46389/37/src/soc/mediatek/mt8192/Ma... 
PS37, Line 61:  
Remove extra space

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Hello Hung-Te Lin, build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu, Nicolas Boichat,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#38).

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

soc/mediatek/mt8192: add spmfw loader

This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,134 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/38

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 38:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46389/37/src/soc/mediatek/mt8192/Ma... 
File src/soc/mediatek/mt8192/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/46389/37/src/soc/mediatek/mt8192/Ma... 
PS37, Line 61:
> Remove extra space

Done

https://review.coreboot.org/c/coreboot/+/46389/37/src/soc/mediatek/mt8192/sp... 
File src/soc/mediatek/mt8192/spm.c:

https://review.coreboot.org/c/coreboot/+/46389/37/src/soc/mediatek/mt8192/sp... 
PS37, Line 645: %s() failed
> SPM: %s: failed in mtlib_init_mcu. […]

Done

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 38: Code-Review+2

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Yidi Lin (Code Review)]

Hello Hung-Te Lin, build bot (Jenkins), Roger Lu, Patrick Georgi, Martin Roth, Roger Lu, Yu-Ping Wu, Nicolas Boichat,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46389

to look at the new patch set (#39).

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

soc/mediatek/mt8192: add spmfw loader

This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,134 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/39

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

Patch Set 39: Code-Review+2

Change in coreboot[master]: soc/mediatek/mt8192: add spmfw loader

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46389 )

Change subject: soc/mediatek/mt8192: add spmfw loader
......................................................................

soc/mediatek/mt8192: add spmfw loader

This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.

BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
     wake up the DUT by powerkey

Signed-off-by: Roger Lu 
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46389
Tested-by: build bot (Jenkins) 
Reviewed-by: Hung-Te Lin 
---
M src/mainboard/google/asurada/mainboard.c
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/spm.h
A src/soc/mediatek/mt8192/spm.c
5 files changed, 1,134 insertions(+), 31 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Hung-Te Lin: Looks good to me, approved

diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c
index e00eb2f..0701c67 100644
--- a/src/mainboard/google/asurada/mainboard.c
+++ b/src/mainboard/google/asurada/mainboard.c
@@ -6,6 +6,7 @@
 #include <device/mmio.h>
 #include <soc/gpio.h>
 #include <soc/regulator.h>
+#include <soc/spm.h>
 #include <soc/usb.h>

#include "gpio.h"
@@ -107,6 +108,9 @@
    setup_usb_host();

register_reset_to_bl31();
+
+	if (spm_init())
+		printk(BIOS_ERR, "spm init fail, system suspend may stuck\n");
 }

static void mainboard_enable(struct device *dev)
diff --git a/src/soc/mediatek/mt8192/Kconfig b/src/soc/mediatek/mt8192/Kconfig
index 8425005..dbb35f6 100644
--- a/src/soc/mediatek/mt8192/Kconfig
+++ b/src/soc/mediatek/mt8192/Kconfig
@@ -45,4 +45,10 @@
      This option enables memory basic compare test to verify the DRAM read
      or write is as expected.

+config SPM_FIRMWARE
+	string
+	default "spm_firmware.bin"
+	help
+	  The file name of the MediaTek SPM firmware.
+
 endif
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 8c7fe0d..3caa1ef 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -43,12 +43,23 @@
 ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += soc.c
+ramstage-y += spm.c
 ramstage-y += ../common/timer.c
 ramstage-y += ../common/uart.c
 ramstage-y += ../common/usb.c usb.c

MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192

+mcu-firmware-files := \
+	$(CONFIG_SPM_FIRMWARE)
+
+$(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \
+	  $(eval $(fw)-file := $(MT8192_BLOB_DIR)/$(fw)) \
+	  $(eval $(fw)-type := raw) \
+	  $(eval $(fw)-compression := $(CBFS_COMPRESS_FLAG)) \
+	  $(if $(wildcard $($(fw)-file)), $(eval cbfs-files-y += $(fw)), ) \
+)
+
 DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram
 $(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf
 $(DRAM_CBFS)-type := stage
diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h
index 73ef798..e2bd3af 100644
--- a/src/soc/mediatek/mt8192/include/soc/spm.h
+++ b/src/soc/mediatek/mt8192/include/soc/spm.h
@@ -4,10 +4,309 @@
 #define SOC_MEDIATEK_MT8192_SPM_H

#include <soc/addressmap.h>
+#include <stdint.h>
 #include <types.h>

/* SPM READ/WRITE CFG */
-#define SPM_PROJECT_CODE	0xb16
+#define SPM_PROJECT_CODE                    0xb16
+#define SPM_REGWR_CFG_KEY                   (SPM_PROJECT_CODE << 16)
+
+/* POWERON_CONFIG_EN (0x10006000+0x000) */
+#define BCLK_CG_EN_LSB                      (1U << 0)       /* 1b */
+
+/* SPM_CLK_CON (0x10006000+0x00C) */
+#define REG_SYSCLK1_SRC_MD2_SRCCLKENA       (1U << 28)      /* 1b */
+
+/* PCM_CON0 (0x10006000+0x018) */
+#define PCM_CK_EN_LSB                       (1U << 2)       /* 1b */
+#define PCM_SW_RESET_LSB                    (1U << 15)      /* 1b */
+
+/* PCM_CON1 (0x10006000+0x01C) */
+#define RG_IM_SLAVE_LSB                     (1U << 0)       /* 1b */
+#define RG_AHBMIF_APBEN_LSB                 (1U << 3)       /* 1b */
+#define RG_PCM_TIMER_EN_LSB                 (1U << 5)       /* 1b */
+#define SPM_EVENT_COUNTER_CLR_LSB           (1U << 6)       /* 1b */
+#define RG_PCM_WDT_WAKE_LSB                 (1U << 9)       /* 1b */
+#define REG_SPM_SRAM_ISOINT_B_LSB           (1U << 11)      /* 1b */
+#define REG_EVENT_LOCK_EN_LSB               (1U << 12)      /* 1b */
+#define REG_MD32_APB_INTERNAL_EN_LSB        (1U << 14)      /* 1b */
+
+/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */
+#define SPM_WAKEUP_EVENT_MASK_BIT0          (1U << 0)       /* 1b */
+#define SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B   (1U << 24)      /* 1b */
+
+/* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */
+#define REG_ALL_DDR_EN_DBC_EN_LSB           (1U << 0)       /* 1b */
+
+/* SPM_DVFS_MISC (0x10006000+0x4AC) */
+#define SPM_DVFS_FORCE_ENABLE_LSB           (1U << 2)       /* 1b */
+#define SPM_DVFSRC_ENABLE_LSB               (1U << 4)       /* 1b */
+
+/* SPM_SW_FLAG_0 (0x10006000+0x600) */
+#define SPM_FLAG_DISABLE_VCORE_DVS          (1U << 3)       /* 1b */
+#define SPM_FLAG_DISABLE_VCORE_DFS          (1U << 4)       /* 1b */
+#define SPM_FLAG_RUN_COMMON_SCENARIO        (1U << 10)      /* 1b */
+
+/* SYS_TIMER_CON (0x10006000+0x98C) */
+#define SYS_TIMER_START_EN_LSB              (1U << 0)       /* 1b */
+
+/* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */
+#define MD32PCM_CFGREG_SW_RSTN_RESET        (1U << 0)       /* 1b */
+
+/**************************************
+ * Config and Parameter
+ **************************************/
+#define POWER_ON_VAL1_DEF                   0x80015860
+#define SPM_WAKEUP_EVENT_MASK_DEF           0xefffffff
+#define SPM_ACK_CHK_3_SEL_HW_S1             0x00350098
+#define SPM_ACK_CHK_3_HW_S1_CNT             0x1
+#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG      0x800
+#define SPM_ACK_CHK_3_CON_EN                0x110
+#define SPM_ACK_CHK_3_CON_CLR_ALL           0x2
+#define SPM_BUS_PROTECT_MASK_B_DEF          0xffffffff
+#define SPM_BUS_PROTECT2_MASK_B_DEF         0xffffffff
+#define MD32PCM_DMA0_CON_VAL                0x0003820e
+#define MD32PCM_DMA0_START_VAL              0x00008000
+#define MD32PCM_CFGREG_SW_RSTN_RUN          0x1
+#define SPM_DVFS_LEVEL_DEF                  0x00000001
+#define SPM_DVS_DFS_LEVEL_DEF               0x00010001
+#define SPM_RESOURCE_ACK_CON0_DEF           0x00000000
+#define SPM_RESOURCE_ACK_CON1_DEF           0x00000000
+#define SPM_RESOURCE_ACK_CON2_DEF           0xcccc4e4e
+#define SPM_RESOURCE_ACK_CON3_DEF           0x00000000
+#define ARMPLL_CLK_SEL_DEF                  0x3ff
+#define DDR_EN_DBC_CON0_DEF                 0x154
+#define SPM_SYSCLK_SETTLE                   0x60fe
+#define SPM_INIT_DONE_US                    20
+#define PCM_WDT_TIMEOUT                     (30 * 32768)
+#define PCM_TIMER_MAX                       (0xffffffff - PCM_WDT_TIMEOUT)
+
+/**************************************
+ * Define and Declare
+ **************************************/
+/* SPM_IRQ_MASK */
+#define ISRM_TWAM                           (1U << 2)
+#define ISRM_PCM_RETURN                     (1U << 3)
+#define ISRM_RET_IRQ_AUX                    0x3fe00
+#define ISRM_ALL_EXC_TWAM                   (ISRM_RET_IRQ_AUX)
+#define ISRM_ALL                            (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
+
+/* SPM_IRQ_STA */
+#define ISRS_TWAM                           (1U << 2)
+#define ISRS_PCM_RETURN                     (1U << 3)
+#define ISRC_TWAM                           ISRS_TWAM
+#define ISRC_ALL_EXC_TWAM                   ISRS_PCM_RETURN
+#define ISRC_ALL                            (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
+
+/* PCM_PWR_IO_EN */
+#define PCM_PWRIO_EN_R0                     (1U << 0)
+#define PCM_PWRIO_EN_R7                     (1U << 7)
+#define PCM_RF_SYNC_R0                      (1U << 16)
+#define PCM_RF_SYNC_R6                      (1U << 22)
+#define PCM_RF_SYNC_R7                      (1U << 23)
+
+/* SPM_SWINT */
+#define PCM_SW_INT_ALL                      0x3ff
+
+struct pwr_ctrl {
+	u32 pcm_flags;
+	u32 pcm_flags_cust;
+	u32 pcm_flags_cust_set;
+	u32 pcm_flags_cust_clr;
+	u32 pcm_flags1;
+	u32 pcm_flags1_cust;
+	u32 pcm_flags1_cust_set;
+	u32 pcm_flags1_cust_clr;
+	u32 timer_val;
+	u32 timer_val_cust;
+	u32 timer_val_ramp_en;
+	u32 timer_val_ramp_en_sec;
+	u32 wake_src;
+	u32 wake_src_cust;
+	u32 wakelock_timer_val;
+	u8 wdt_disable;
+
+	/* Auto-gen Start */
+
+	/* SPM_CLK_CON */
+	u8 reg_srcclken0_ctl;
+	u8 reg_srcclken1_ctl;
+	u8 reg_spm_lock_infra_dcm;
+	u8 reg_srcclken_mask;
+	u8 reg_md1_c32rm_en;
+	u8 reg_md2_c32rm_en;
+	u8 reg_clksq0_sel_ctrl;
+	u8 reg_clksq1_sel_ctrl;
+	u8 reg_srcclken0_en;
+	u8 reg_srcclken1_en;
+	u32 reg_sysclk0_src_mask_b;
+	u32 reg_sysclk1_src_mask_b;
+
+	/* SPM_AP_STANDBY_CON */
+	u8 reg_wfi_op;
+	u8 reg_wfi_type;
+	u8 reg_mp0_cputop_idle_mask;
+	u8 reg_mp1_cputop_idle_mask;
+	u8 reg_mcusys_idle_mask;
+	u8 reg_md_apsrc_1_sel;
+	u8 reg_md_apsrc_0_sel;
+	u8 reg_conn_apsrc_sel;
+
+	/* SPM_SRC6_MASK */
+	u8 reg_dpmaif_srcclkena_mask_b;
+	u8 reg_dpmaif_infra_req_mask_b;
+	u8 reg_dpmaif_apsrc_req_mask_b;
+	u8 reg_dpmaif_vrf18_req_mask_b;
+	u8 reg_dpmaif_ddr_en_mask_b;
+
+	/* SPM_SRC_REQ */
+	u8 reg_spm_apsrc_req;
+	u8 reg_spm_f26m_req;
+	u8 reg_spm_infra_req;
+	u8 reg_spm_vrf18_req;
+	u8 reg_spm_ddr_en_req;
+	u8 reg_spm_dvfs_req;
+	u8 reg_spm_sw_mailbox_req;
+	u8 reg_spm_sspm_mailbox_req;
+	u8 reg_spm_adsp_mailbox_req;
+	u8 reg_spm_scp_mailbox_req;
+
+	/* SPM_SRC_MASK */
+	u8 reg_md_srcclkena_0_mask_b;
+	u8 reg_md_srcclkena2infra_req_0_mask_b;
+	u8 reg_md_apsrc2infra_req_0_mask_b;
+	u8 reg_md_apsrc_req_0_mask_b;
+	u8 reg_md_vrf18_req_0_mask_b;
+	u8 reg_md_ddr_en_0_mask_b;
+	u8 reg_md_srcclkena_1_mask_b;
+	u8 reg_md_srcclkena2infra_req_1_mask_b;
+	u8 reg_md_apsrc2infra_req_1_mask_b;
+	u8 reg_md_apsrc_req_1_mask_b;
+	u8 reg_md_vrf18_req_1_mask_b;
+	u8 reg_md_ddr_en_1_mask_b;
+	u8 reg_conn_srcclkena_mask_b;
+	u8 reg_conn_srcclkenb_mask_b;
+	u8 reg_conn_infra_req_mask_b;
+	u8 reg_conn_apsrc_req_mask_b;
+	u8 reg_conn_vrf18_req_mask_b;
+	u8 reg_conn_ddr_en_mask_b;
+	u8 reg_conn_vfe28_mask_b;
+	u8 reg_srcclkeni0_srcclkena_mask_b;
+	u8 reg_srcclkeni0_infra_req_mask_b;
+	u8 reg_srcclkeni1_srcclkena_mask_b;
+	u8 reg_srcclkeni1_infra_req_mask_b;
+	u8 reg_srcclkeni2_srcclkena_mask_b;
+	u8 reg_srcclkeni2_infra_req_mask_b;
+	u8 reg_infrasys_apsrc_req_mask_b;
+	u8 reg_infrasys_ddr_en_mask_b;
+	u8 reg_md32_srcclkena_mask_b;
+	u8 reg_md32_infra_req_mask_b;
+	u8 reg_md32_apsrc_req_mask_b;
+	u8 reg_md32_vrf18_req_mask_b;
+	u8 reg_md32_ddr_en_mask_b;
+
+	/* SPM_SRC2_MASK */
+	u8 reg_scp_srcclkena_mask_b;
+	u8 reg_scp_infra_req_mask_b;
+	u8 reg_scp_apsrc_req_mask_b;
+	u8 reg_scp_vrf18_req_mask_b;
+	u8 reg_scp_ddr_en_mask_b;
+	u8 reg_audio_dsp_srcclkena_mask_b;
+	u8 reg_audio_dsp_infra_req_mask_b;
+	u8 reg_audio_dsp_apsrc_req_mask_b;
+	u8 reg_audio_dsp_vrf18_req_mask_b;
+	u8 reg_audio_dsp_ddr_en_mask_b;
+	u8 reg_ufs_srcclkena_mask_b;
+	u8 reg_ufs_infra_req_mask_b;
+	u8 reg_ufs_apsrc_req_mask_b;
+	u8 reg_ufs_vrf18_req_mask_b;
+	u8 reg_ufs_ddr_en_mask_b;
+	u8 reg_disp0_apsrc_req_mask_b;
+	u8 reg_disp0_ddr_en_mask_b;
+	u8 reg_disp1_apsrc_req_mask_b;
+	u8 reg_disp1_ddr_en_mask_b;
+	u8 reg_gce_infra_req_mask_b;
+	u8 reg_gce_apsrc_req_mask_b;
+	u8 reg_gce_vrf18_req_mask_b;
+	u8 reg_gce_ddr_en_mask_b;
+	u8 reg_apu_srcclkena_mask_b;
+	u8 reg_apu_infra_req_mask_b;
+	u8 reg_apu_apsrc_req_mask_b;
+	u8 reg_apu_vrf18_req_mask_b;
+	u8 reg_apu_ddr_en_mask_b;
+	u8 reg_cg_check_srcclkena_mask_b;
+	u8 reg_cg_check_apsrc_req_mask_b;
+	u8 reg_cg_check_vrf18_req_mask_b;
+	u8 reg_cg_check_ddr_en_mask_b;
+
+	/* SPM_SRC3_MASK */
+	u8 reg_dvfsrc_event_trigger_mask_b;
+	u8 reg_sw2spm_int0_mask_b;
+	u8 reg_sw2spm_int1_mask_b;
+	u8 reg_sw2spm_int2_mask_b;
+	u8 reg_sw2spm_int3_mask_b;
+	u8 reg_sc_adsp2spm_wakeup_mask_b;
+	u8 reg_sc_sspm2spm_wakeup_mask_b;
+	u8 reg_sc_scp2spm_wakeup_mask_b;
+	u8 reg_csyspwrreq_mask;
+	u8 reg_spm_srcclkena_reserved_mask_b;
+	u8 reg_spm_infra_req_reserved_mask_b;
+	u8 reg_spm_apsrc_req_reserved_mask_b;
+	u8 reg_spm_vrf18_req_reserved_mask_b;
+	u8 reg_spm_ddr_en_reserved_mask_b;
+	u8 reg_mcupm_srcclkena_mask_b;
+	u8 reg_mcupm_infra_req_mask_b;
+	u8 reg_mcupm_apsrc_req_mask_b;
+	u8 reg_mcupm_vrf18_req_mask_b;
+	u8 reg_mcupm_ddr_en_mask_b;
+	u8 reg_msdc0_srcclkena_mask_b;
+	u8 reg_msdc0_infra_req_mask_b;
+	u8 reg_msdc0_apsrc_req_mask_b;
+	u8 reg_msdc0_vrf18_req_mask_b;
+	u8 reg_msdc0_ddr_en_mask_b;
+	u8 reg_msdc1_srcclkena_mask_b;
+	u8 reg_msdc1_infra_req_mask_b;
+	u8 reg_msdc1_apsrc_req_mask_b;
+	u8 reg_msdc1_vrf18_req_mask_b;
+	u8 reg_msdc1_ddr_en_mask_b;
+
+	/* SPM_SRC4_MASK */
+	u32 ccif_event_mask_b;
+	u8 reg_bak_psri_srcclkena_mask_b;
+	u8 reg_bak_psri_infra_req_mask_b;
+	u8 reg_bak_psri_apsrc_req_mask_b;
+	u8 reg_bak_psri_vrf18_req_mask_b;
+	u8 reg_bak_psri_ddr_en_mask_b;
+	u8 reg_dramc0_md32_infra_req_mask_b;
+	u8 reg_dramc0_md32_vrf18_req_mask_b;
+	u8 reg_dramc1_md32_infra_req_mask_b;
+	u8 reg_dramc1_md32_vrf18_req_mask_b;
+	u8 reg_conn_srcclkenb2pwrap_mask_b;
+	u8 reg_dramc0_md32_wakeup_mask;
+	u8 reg_dramc1_md32_wakeup_mask;
+
+	/* SPM_SRC5_MASK */
+	u32 reg_mcusys_merge_apsrc_req_mask_b;
+	u32 reg_mcusys_merge_ddr_en_mask_b;
+	u8 reg_msdc2_srcclkena_mask_b;
+	u8 reg_msdc2_infra_req_mask_b;
+	u8 reg_msdc2_apsrc_req_mask_b;
+	u8 reg_msdc2_vrf18_req_mask_b;
+	u8 reg_msdc2_ddr_en_mask_b;
+	u8 reg_pcie_srcclkena_mask_b;
+	u8 reg_pcie_infra_req_mask_b;
+	u8 reg_pcie_apsrc_req_mask_b;
+	u8 reg_pcie_vrf18_req_mask_b;
+	u8 reg_pcie_ddr_en_mask_b;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	u32 reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	u32 reg_ext_wakeup_event_mask;
+
+	/* Auto-gen End */
+};

enum {
    DISP_PWR_STA_MASK	= 0x1 << 20,
@@ -34,14 +333,14 @@
    u32 pcm_timer_val;
    u32 pcm_wdt_val;
    u32 spm_src6_mask;
-	u32 reserved1[1];
-	u32 spm_sw_rst_con;	/* 0x0040 */
+	u32 reserved0;
+	u32 spm_sw_rst_con;
    u32 spm_sw_rst_con_set;
    u32 spm_sw_rst_con_clr;
    u32 vs1_psr_mask_b;
    u32 vs2_psr_mask_b;
-	u32 reserved2[12];
-	u32 md32_clk_con;	/* 0x0084 */
+	u32 reserved1[12];
+	u32 md32_clk_con;
    u32 spm_sram_rsv_con;
    u32 spm_swint;
    u32 spm_swint_set;
@@ -77,27 +376,27 @@
    u32 pcm_reg6_data;
    u32 pcm_reg7_data;
    u32 pcm_reg13_data;
-	u32 src_req_sta_0;
-	u32 src_req_sta_1;
-	u32 src_req_sta_2;
+	u32 src_req_sta0;
+	u32 src_req_sta1;
+	u32 src_req_sta2;
    u32 pcm_timer_out;
    u32 pcm_wdt_out;
    u32 spm_irq_sta;
-	u32 src_req_sta_4;
+	u32 src_req_sta4;
    u32 md32pcm_wakeup_sta;
    u32 md32pcm_event_sta;
    u32 spm_wakeup_sta;
    u32 spm_wakeup_ext_sta;
    u32 spm_wakeup_misc;
    u32 mm_dvfs_halt;
-	u32 reserved3[2];
-	u32 bus_protect_rdy;	/* 0x0150 */
+	u32 reserved2[2];
+	u32 bus_protect_rdy;
    u32 bus_protect1_rdy;
    u32 bus_protect2_rdy;
    u32 bus_protect3_rdy;
    u32 subsys_idle_sta;
    u32 pcm_sta;
-	u32 src_req_sta_3;
+	u32 src_req_sta3;
    u32 pwr_status;
    u32 pwr_status_2nd;
    u32 cpu_pwr_status;
@@ -109,15 +408,15 @@
    u32 spm_ddren_event_count_sta;
    u32 md32pcm_sta;
    u32 md32pcm_pc;
-	u32 reserved4[3];
-	u32 dvfsrc_event_sta;	/* 0x01a4 */
+	u32 reserved3[3];
+	u32 dvfsrc_event_sta;
    u32 bus_protect4_rdy;
    u32 bus_protect5_rdy;
    u32 bus_protect6_rdy;
    u32 bus_protect7_rdy;
    u32 bus_protect8_rdy;
-	u32 reserved5[5];
-	u32 spm_twam_last_sta0;	/* 0x01d0 */
+	u32 reserved4[5];
+	u32 spm_twam_last_sta0;
    u32 spm_twam_last_sta1;
    u32 spm_twam_last_sta2;
    u32 spm_twam_last_sta3;
@@ -139,8 +438,8 @@
    u32 spm_cpu5_pwr_con;
    u32 spm_cpu6_pwr_con;
    u32 spm_cpu7_pwr_con;
-	u32 reserved6[1];
-	u32 armpll_clk_con;	/* 0x022c */
+	u32 reserved5;
+	u32 armpll_clk_con;
    u32 mcusys_idle_sta;
    u32 gic_wakeup_sta;
    u32 cpu_spare_con;
@@ -150,8 +449,8 @@
    u32 ext_int_wakeup_req;
    u32 ext_int_wakeup_req_set;
    u32 ext_int_wakeup_req_clr;
-	u32 reserved7[3];
-	u32 mp0_cpu0_irq_mask;	/* 0x0260 */
+	u32 reserved6[3];
+	u32 mp0_cpu0_irq_mask;
    u32 mp0_cpu1_irq_mask;
    u32 mp0_cpu2_irq_mask;
    u32 mp0_cpu3_irq_mask;
@@ -169,8 +468,8 @@
    u32 mp0_cpu7_wfi_en;
    u32 root_cputop_addr;
    u32 root_core_addr;
-	u32 reserved8[10];
-	u32 spm2sw_mailbox_0;	/* 0x02d0 */
+	u32 reserved7[10];
+	u32 spm2sw_mailbox_0;
    u32 spm2sw_mailbox_1;
    u32 spm2sw_mailbox_2;
    u32 spm2sw_mailbox_3;
@@ -227,22 +526,151 @@
    u32 debugtop_sram_con;
    u32 dp_tx_pwr_con;
    u32 dpmaif_sram_con;
-	u32 dpy_shu2_sram_con;
+	u32 dpy_shu2_con;
    u32 dramc_mcu2_sram_con;
    u32 dramc_mcu_sram_con;
    u32 mcupm_pwr_con;
    u32 dpy2_pwr_con;
    u32 peri_pwr_con;
+	u32 reserved8[13];
+	u32 spm_mem_ck_sel;
+	u32 spm_bus_protect_mask_b;
+	u32 spm_bus_protect1_mask_b;
+	u32 spm_bus_protect2_mask_b;
+	u32 spm_bus_protect3_mask_b;
+	u32 spm_bus_protect4_mask_b;
+	u32 spm_emi_bw_mode;
+	u32 ap2md_peer_wakeup;
+	u32 ulposc_con;
+	u32 spm2mm_con;
+	u32 spm_bus_protect5_mask_b;
+	u32 spm2mcupm_con;
+	u32 ap_mdsrc_req;
+	u32 spm2emi_enter_ulpm;
+	u32 spm2md_dvfs_con;
+	u32 md2spm_dvfs_con;
+	u32 spm_bus_protect6_mask_b;
+	u32 spm_bus_protect7_mask_b;
+	u32 spm_bus_protect8_mask_b;
+	u32 spm_pll_con;
+	u32 cpu_dvfs_req;
+	u32 spm_dram_mcu_sw_con0;
+	u32 spm_dram_mcu_sw_con1;
+	u32 spm_dram_mcu_sw_con2;
+	u32 spm_dram_mcu_sw_con3;
+	u32 spm_dram_mcu_sw_con4;
+	u32 spm_dram_mcu_sta_0;
+	u32 spm_dram_mcu_sta_1;
+	u32 spm_dram_mcu_sta_2;
+	u32 spm_dram_mcu_sw_sel_0;
+	u32 relay_dvfs_level;
+	u32 reserved9;
+	u32 dramc_dpy_clk_sw_con_0;
+	u32 dramc_dpy_clk_sw_con_1;
+	u32 dramc_dpy_clk_sw_con_2;
+	u32 dramc_dpy_clk_sw_con_3;
+	u32 dramc_dpy_clk_sw_sel_0;
+	u32 dramc_dpy_clk_sw_sel_1;
+	u32 dramc_dpy_clk_sw_sel_2;
+	u32 dramc_dpy_clk_sw_sel_3;
+	u32 dramc_dpy_clk_spm_con;
+	u32 spm_dvfs_level;
+	u32 spm_cirq_con;
+	u32 spm_dvfs_misc;
+	u32 spm_vs1_vs2_rc_con;
+	u32 rg_module_sw_cg_0_mask_req_0;
+	u32 rg_module_sw_cg_0_mask_req_1;
+	u32 rg_module_sw_cg_0_mask_req_2;
+	u32 rg_module_sw_cg_1_mask_req_0;
+	u32 rg_module_sw_cg_1_mask_req_1;
+	u32 rg_module_sw_cg_1_mask_req_2;
+	u32 rg_module_sw_cg_2_mask_req_0;
+	u32 rg_module_sw_cg_2_mask_req_1;
+	u32 rg_module_sw_cg_2_mask_req_2;
+	u32 rg_module_sw_cg_3_mask_req_0;
+	u32 rg_module_sw_cg_3_mask_req_1;
+	u32 rg_module_sw_cg_3_mask_req_2;
+	u32 pwr_status_mask_req_0;
+	u32 pwr_status_mask_req_1;
+	u32 pwr_status_mask_req_2;
+	u32 spm_cg_check_con;
+	u32 spm_src_rdy_sta;
+	u32 spm_dvs_dfs_level;
+	u32 spm_force_dvfs;
+	u32 reserved10[64];
+	u32 spm_sw_flag_0;
+	u32 spm_sw_debug_0;
+	u32 spm_sw_flag_1;
+	u32 reserved11[8];
+	u32 spm_sw_rsv_7;
+	u32 spm_sw_rsv_8;
+	u32 reserved12[203];
+	u32 spm_ack_chk_con_3;
+	u32 spm_ack_chk_pc_3;
+	u32 spm_ack_chk_sel_3;
+	u32 spm_ack_chk_timer_3;
+	u32 reserved13[7];
+	u32 sys_timer_con;
+	u32 reserved14[28];
+	u32 md32pcm_cfgreg_sw_rstn;
+	u32 reserved15[127];
+	u32 md32pcm_dma0_src;
+	u32 md32pcm_dma0_dst;
+	u32 md32pcm_dma0_wppt;
+	u32 md32pcm_dma0_wpto;
+	u32 md32pcm_dma0_count;
+	u32 md32pcm_dma0_con;
+	u32 md32pcm_dma0_start;
+	u32 reserved16[2];
+	u32 md32pcm_dma0_rlct;
 };
-
-check_member(mtk_spm_regs, md32_clk_con, 0x0084);
-check_member(mtk_spm_regs, bus_protect_rdy, 0x0150);
-check_member(mtk_spm_regs, dvfsrc_event_sta, 0x01a4);
-check_member(mtk_spm_regs, spm_twam_last_sta0, 0x01d0);
-check_member(mtk_spm_regs, mp0_cpu0_irq_mask, 0x0260);
-check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x02d0);
-check_member(mtk_spm_regs, peri_pwr_con, 0x03c8);
+check_member(mtk_spm_regs, poweron_config_set, 0x0);
+check_member(mtk_spm_regs, vs2_psr_mask_b, 0x50);
+check_member(mtk_spm_regs, md32_clk_con, 0x84);
+check_member(mtk_spm_regs, mm_dvfs_halt, 0x144);
+check_member(mtk_spm_regs, bus_protect_rdy, 0x150);
+check_member(mtk_spm_regs, md32pcm_pc, 0x194);
+check_member(mtk_spm_regs, dvfsrc_event_sta, 0x1a4);
+check_member(mtk_spm_regs, bus_protect8_rdy, 0x1b8);
+check_member(mtk_spm_regs, spm_twam_last_sta0, 0x1d0);
+check_member(mtk_spm_regs, ext_int_wakeup_req_clr, 0x250);
+check_member(mtk_spm_regs, mp0_cpu0_irq_mask, 0x260);
+check_member(mtk_spm_regs, root_core_addr, 0x2a4);
+check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x2d0);
+check_member(mtk_spm_regs, peri_pwr_con, 0x3c8);
+check_member(mtk_spm_regs, spm_mem_ck_sel, 0x400);
+check_member(mtk_spm_regs, spm_force_dvfs, 0x4fc);
+check_member(mtk_spm_regs, spm_sw_flag_0, 0x600);
+check_member(mtk_spm_regs, spm_sw_flag_1, 0x608);
+check_member(mtk_spm_regs, spm_sw_rsv_7, 0x62c);
+check_member(mtk_spm_regs, spm_sw_rsv_8, 0x630);
+check_member(mtk_spm_regs, spm_ack_chk_con_3, 0x960);
+check_member(mtk_spm_regs, spm_ack_chk_timer_3, 0x96c);
+check_member(mtk_spm_regs, sys_timer_con, 0x98c);
+check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xa00);
+check_member(mtk_spm_regs, md32pcm_dma0_src, 0xc00);
+check_member(mtk_spm_regs, md32pcm_dma0_dst, 0xc04);
+check_member(mtk_spm_regs, md32pcm_dma0_wppt, 0xc08);
+check_member(mtk_spm_regs, md32pcm_dma0_wpto, 0xc0c);
+check_member(mtk_spm_regs, md32pcm_dma0_count, 0xc10);
+check_member(mtk_spm_regs, md32pcm_dma0_con, 0xc14);
+check_member(mtk_spm_regs, md32pcm_dma0_start, 0xc18);
+check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xc24);

static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;

+struct pcm_desc {
+	u32 pmem_words;
+	u32 total_words;
+	u32 pmem_start;
+	u32 dmem_start;
+};
+
+struct dyna_load_pcm {
+	u8 *buf;		/* binary array */
+	struct pcm_desc desc;
+};
+
+int spm_init(void);
+
 #endif  /* SOC_MEDIATEK_MT8192_SPM_H */
diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c
new file mode 100644
index 0000000..f080a11
--- /dev/null
+++ b/src/soc/mediatek/mt8192/spm.c
@@ -0,0 +1,654 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <soc/mcu_common.h>
+#include <soc/spm.h>
+#include <soc/symbols.h>
+#include <timer.h>
+
+#define SPM_SYSTEM_BASE_OFFSET	0x40000000
+#define SPMFW_HEADER_SIZE	16
+
+static const struct pwr_ctrl spm_init_ctrl = {
+	/* Auto-gen Start */
+
+	.pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS |
+		     SPM_FLAG_RUN_COMMON_SCENARIO,
+
+	/* SPM_SRC6_MASK */
+	.reg_dpmaif_srcclkena_mask_b = 1,
+	.reg_dpmaif_infra_req_mask_b = 1,
+	.reg_dpmaif_apsrc_req_mask_b = 1,
+	.reg_dpmaif_vrf18_req_mask_b = 1,
+	.reg_dpmaif_ddr_en_mask_b    = 1,
+
+	/* SPM_SRC_REQ */
+	.reg_spm_ddr_en_req = 1,
+
+	/* SPM_SRC_MASK */
+	.reg_md_srcclkena_0_mask_b = 1,
+	.reg_md_apsrc2infra_req_0_mask_b = 1,
+	.reg_md_apsrc_req_0_mask_b = 1,
+	.reg_md_vrf18_req_0_mask_b = 1,
+	.reg_md_ddr_en_0_mask_b = 1,
+	.reg_conn_srcclkena_mask_b = 1,
+	.reg_conn_infra_req_mask_b = 1,
+	.reg_conn_apsrc_req_mask_b = 1,
+	.reg_conn_vrf18_req_mask_b = 1,
+	.reg_conn_ddr_en_mask_b = 1,
+	.reg_srcclkeni0_srcclkena_mask_b = 1,
+	.reg_srcclkeni0_infra_req_mask_b = 1,
+	.reg_infrasys_ddr_en_mask_b = 1,
+	.reg_md32_srcclkena_mask_b = 1,
+	.reg_md32_infra_req_mask_b = 1,
+	.reg_md32_apsrc_req_mask_b = 1,
+	.reg_md32_vrf18_req_mask_b = 1,
+	.reg_md32_ddr_en_mask_b = 1,
+
+	/* SPM_SRC2_MASK */
+	.reg_scp_srcclkena_mask_b = 1,
+	.reg_scp_infra_req_mask_b = 1,
+	.reg_scp_apsrc_req_mask_b = 1,
+	.reg_scp_vrf18_req_mask_b = 1,
+	.reg_scp_ddr_en_mask_b = 1,
+	.reg_audio_dsp_srcclkena_mask_b = 1,
+	.reg_audio_dsp_infra_req_mask_b = 1,
+	.reg_audio_dsp_apsrc_req_mask_b = 1,
+	.reg_audio_dsp_vrf18_req_mask_b = 1,
+	.reg_audio_dsp_ddr_en_mask_b = 1,
+	.reg_ufs_srcclkena_mask_b = 1,
+	.reg_ufs_infra_req_mask_b = 1,
+	.reg_ufs_apsrc_req_mask_b = 1,
+	.reg_ufs_vrf18_req_mask_b = 1,
+	.reg_ufs_ddr_en_mask_b = 1,
+	.reg_disp0_apsrc_req_mask_b = 1,
+	.reg_disp0_ddr_en_mask_b = 1,
+	.reg_disp1_apsrc_req_mask_b = 1,
+	.reg_disp1_ddr_en_mask_b = 1,
+	.reg_gce_infra_req_mask_b = 1,
+	.reg_gce_apsrc_req_mask_b = 1,
+	.reg_gce_vrf18_req_mask_b = 1,
+	.reg_gce_ddr_en_mask_b = 1,
+	.reg_apu_srcclkena_mask_b = 1,
+	.reg_apu_infra_req_mask_b = 1,
+	.reg_apu_apsrc_req_mask_b = 1,
+	.reg_apu_vrf18_req_mask_b = 1,
+	.reg_apu_ddr_en_mask_b = 1,
+
+	/* SPM_SRC3_MASK */
+	.reg_dvfsrc_event_trigger_mask_b = 1,
+	.reg_csyspwrreq_mask = 1,
+	.reg_mcupm_srcclkena_mask_b = 1,
+	.reg_mcupm_infra_req_mask_b = 1,
+	.reg_mcupm_apsrc_req_mask_b = 1,
+	.reg_mcupm_vrf18_req_mask_b = 1,
+	.reg_mcupm_ddr_en_mask_b = 1,
+	.reg_msdc0_srcclkena_mask_b = 1,
+	.reg_msdc0_infra_req_mask_b = 1,
+	.reg_msdc0_apsrc_req_mask_b = 1,
+	.reg_msdc0_vrf18_req_mask_b = 1,
+	.reg_msdc0_ddr_en_mask_b = 1,
+	.reg_msdc1_srcclkena_mask_b = 1,
+	.reg_msdc1_infra_req_mask_b = 1,
+	.reg_msdc1_apsrc_req_mask_b = 1,
+	.reg_msdc1_vrf18_req_mask_b = 1,
+	.reg_msdc1_ddr_en_mask_b = 1,
+
+	/* SPM_SRC4_MASK */
+	.ccif_event_mask_b = 0xFFF,
+	.reg_dramc0_md32_infra_req_mask_b = 1,
+	.reg_dramc1_md32_infra_req_mask_b = 1,
+	.reg_dramc0_md32_wakeup_mask = 1,
+	.reg_dramc1_md32_wakeup_mask = 1,
+
+	/* SPM_SRC5_MASK */
+	.reg_mcusys_merge_apsrc_req_mask_b = 0x11,
+	.reg_mcusys_merge_ddr_en_mask_b = 0x11,
+	.reg_msdc2_srcclkena_mask_b = 1,
+	.reg_msdc2_infra_req_mask_b = 1,
+	.reg_msdc2_apsrc_req_mask_b = 1,
+	.reg_msdc2_vrf18_req_mask_b = 1,
+	.reg_msdc2_ddr_en_mask_b = 1,
+	.reg_pcie_srcclkena_mask_b = 1,
+	.reg_pcie_infra_req_mask_b = 1,
+	.reg_pcie_apsrc_req_mask_b = 1,
+	.reg_pcie_vrf18_req_mask_b = 1,
+	.reg_pcie_ddr_en_mask_b = 1,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	.reg_wakeup_event_mask = 0xEFFFFFFF,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+	/* Auto-gen End */
+};
+
+static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
+{
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	write32(&mtk_spm->spm_ap_standby_con,
+		((pwrctrl->reg_wfi_op & 0x1) << 0) |
+		((pwrctrl->reg_wfi_type & 0x1) << 1) |
+		((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
+		((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
+		((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
+		((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
+		((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
+		((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
+
+	/* SPM_SRC6_MASK */
+	write32(&mtk_spm->spm_src6_mask,
+		((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_dpmaif_ddr_en_mask_b & 0x1) << 4));
+
+	/* SPM_SRC_REQ */
+	write32(&mtk_spm->spm_src_req,
+		((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
+		((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
+		((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
+		((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
+		((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
+		((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+		((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+		((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+		((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+		((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+	/* SPM_SRC_MASK */
+	write32(&mtk_spm->spm_src_mask,
+		((pwrctrl->reg_md_srcclkena_0_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_md_srcclkena2infra_req_0_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_md_apsrc2infra_req_0_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_md_apsrc_req_0_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_md_vrf18_req_0_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_md_ddr_en_0_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_md_srcclkena_1_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_md_srcclkena2infra_req_1_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_md_apsrc2infra_req_1_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_md_apsrc_req_1_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_md_vrf18_req_1_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_md_ddr_en_1_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_conn_ddr_en_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_srcclkeni0_srcclkena_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_srcclkeni0_infra_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_srcclkeni1_srcclkena_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_srcclkeni1_infra_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_srcclkeni2_srcclkena_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_srcclkeni2_infra_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_md32_srcclkena_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_md32_infra_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_md32_apsrc_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_md32_vrf18_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_md32_ddr_en_mask_b & 0x1) << 31));
+
+	/* SPM_SRC2_MASK */
+	write32(&mtk_spm->spm_src2_mask,
+		((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_gce_ddr_en_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_cg_check_ddr_en_mask_b & 0x1) << 31));
+
+	/* SPM_SRC3_MASK */
+	write32(&mtk_spm->spm_src3_mask,
+		((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_sw2spm_int0_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_sw2spm_int1_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_sw2spm_int2_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_sw2spm_int3_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_sc_adsp2spm_wakeup_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_sc_sspm2spm_wakeup_mask_b & 0xf) << 6) |
+		((pwrctrl->reg_sc_scp2spm_wakeup_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_csyspwrreq_mask & 0x1) << 11) |
+		((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_mcupm_ddr_en_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 31));
+
+	/* SPM_SRC4_MASK */
+	write32(&mtk_spm->spm_src4_mask,
+		((pwrctrl->ccif_event_mask_b & 0xffff) << 0) |
+		((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_dramc0_md32_infra_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_dramc0_md32_vrf18_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_dramc1_md32_infra_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_dramc1_md32_vrf18_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_dramc0_md32_wakeup_mask & 0x1) << 26) |
+		((pwrctrl->reg_dramc1_md32_wakeup_mask & 0x1) << 27));
+
+	/* SPM_SRC5_MASK */
+	write32(&mtk_spm->spm_src5_mask,
+		((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
+		((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) |
+		((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_pcie_ddr_en_mask_b & 0x1) << 27));
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	write32(&mtk_spm->spm_wakeup_event_mask,
+		((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	write32(&mtk_spm->spm_wakeup_event_ext_mask,
+		((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
+
+	/* Auto-gen End */
+}
+
+static void spm_register_init(void)
+{
+	/* Enable register control */
+	write32(&mtk_spm->poweron_config_set,
+		SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+
+	/* Init power control register */
+	write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF);
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+
+	/* Reset PCM */
+	write32(&mtk_spm->pcm_con0,
+		SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
+	write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+	write32(&mtk_spm->pcm_con1,
+		SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
+		REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
+		REG_MD32_APB_INTERNAL_EN_LSB);
+
+	/* Initial SPM CLK control register */
+	setbits32(&mtk_spm->spm_clk_con, REG_SYSCLK1_SRC_MD2_SRCCLKENA);
+
+	/* Clean wakeup event raw status */
+	write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF);
+
+	/* Clean ISR status */
+	write32(&mtk_spm->spm_irq_mask, ISRM_ALL);
+	write32(&mtk_spm->spm_irq_sta, ISRC_ALL);
+	write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL);
+
+	/* Init r7 with POWER_ON_VAL1 */
+	write32(&mtk_spm->pcm_reg_data_ini,
+		read32(&mtk_spm->spm_power_on_val1));
+	write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+
+	/* DDR EN de-bounce length to 5us */
+	write32(&mtk_spm->ddr_en_dbc_con0, DDR_EN_DBC_CON0_DEF);
+	write32(&mtk_spm->ddr_en_dbc_con1, REG_ALL_DDR_EN_DBC_EN_LSB);
+
+	/* Configure ARMPLL Control Mode for MCDI */
+	write32(&mtk_spm->armpll_clk_sel, ARMPLL_CLK_SEL_DEF);
+
+	/* Init for SPM Resource ACK */
+	write32(&mtk_spm->spm_resource_ack_con0, SPM_RESOURCE_ACK_CON0_DEF);
+	write32(&mtk_spm->spm_resource_ack_con1, SPM_RESOURCE_ACK_CON1_DEF);
+	write32(&mtk_spm->spm_resource_ack_con2, SPM_RESOURCE_ACK_CON2_DEF);
+	write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF);
+
+	/* Init VCORE DVFS Status */
+	clrsetbits32(&mtk_spm->spm_dvfs_misc,
+		     SPM_DVFS_FORCE_ENABLE_LSB, SPM_DVFSRC_ENABLE_LSB);
+	write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF);
+	write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF);
+
+	write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1);
+	write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT);
+
+	/* Apm hw s1 state monitor pause */
+	clrsetbits32(&mtk_spm->spm_ack_chk_con_3,
+		     SPM_ACK_CHK_3_CON_EN,
+		     SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
+		     SPM_ACK_CHK_3_CON_CLR_ALL);
+}
+
+static void spm_set_sysclk_settle(void)
+{
+	write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE);
+}
+
+static void spm_code_swapping(void)
+{
+	u32 mask;
+
+	mask = read32(&mtk_spm->spm_wakeup_event_mask);
+	write32(&mtk_spm->spm_wakeup_event_mask,
+		mask & ~SPM_WAKEUP_EVENT_MASK_BIT0);
+	write32(&mtk_spm->spm_cpu_wakeup_event, 1);
+	write32(&mtk_spm->spm_cpu_wakeup_event, 0);
+	write32(&mtk_spm->spm_wakeup_event_mask, mask);
+}
+
+static void spm_reset_and_init_pcm(void)
+{
+	bool first_load_fw = true;
+
+	/* Check the SPM FW is run or not */
+	if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) &
+	    MD32PCM_CFGREG_SW_RSTN_RUN)
+		first_load_fw = false;
+
+	if (!first_load_fw) {
+		spm_code_swapping();
+		/* Backup PCM r0 -> SPM_POWER_ON_VAL0 before reset PCM */
+		write32(&mtk_spm->spm_power_on_val0,
+			read32(&mtk_spm->pcm_reg0_data));
+	}
+
+	/* Disable r0 and r7 to control power */
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+
+	/* Disable pcm timer after leaving FW */
+	clrsetbits32(&mtk_spm->pcm_con1,
+		     RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
+
+	/* Reset PCM */
+	write32(&mtk_spm->pcm_con0,
+		SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
+	write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+
+	/* Init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */
+	clrsetbits32(&mtk_spm->pcm_con1, ~RG_PCM_WDT_WAKE_LSB,
+		     SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
+		     REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB |
+		     REG_MD32_APB_INTERNAL_EN_LSB);
+}
+
+static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
+{
+	uintptr_t ptr;
+	u32 dmem_words;
+	u32 pmem_words;
+	u32 total_words;
+	u32 pmem_start;
+	u32 dmem_start;
+
+	ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET;
+	pmem_words = pcm->desc.pmem_words;
+	total_words = pcm->desc.total_words;
+	dmem_words = total_words - pmem_words;
+	pmem_start = pcm->desc.pmem_start;
+	dmem_start = pcm->desc.dmem_start;
+
+	printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n",
+	       __func__, (long)ptr, pmem_words, dmem_words);
+
+	/* DMA needs 16-byte aligned source data. */
+	assert(ptr % 16 == 0);
+	/* Program/Data must also be 16-byte (4-word) aligned. */
+	assert(pmem_words % 4 == 0);
+	assert(dmem_words % 4 == 0);
+
+	write32(&mtk_spm->md32pcm_dma0_src, ptr);
+	write32(&mtk_spm->md32pcm_dma0_dst, pmem_start);
+	write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words);
+	write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start);
+	write32(&mtk_spm->md32pcm_dma0_count, total_words);
+	write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL);
+	write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL);
+
+	setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+}
+
+static void spm_init_pcm_register(void)
+{
+	/* Init r0 with POWER_ON_VAL0 */
+	write32(&mtk_spm->pcm_reg_data_ini,
+		read32(&mtk_spm->spm_power_on_val0));
+	write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0);
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+
+	/* Init r7 with POWER_ON_VAL1 */
+	write32(&mtk_spm->pcm_reg_data_ini,
+		read32(&mtk_spm->spm_power_on_val1));
+	write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
+	write32(&mtk_spm->pcm_pwr_io_en, 0);
+}
+
+static void spm_parse_firmware(struct mtk_mcu *mcu)
+{
+	size_t file_size, copy_size;
+	int offset;
+	u16 firmware_size;
+
+	struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv;
+	file_size = mcu->run_size;
+
+	/*
+	 * spmfw layout:
+	 *   u16 firmware_size
+	 *   u32 binary[firmware_size]
+	 *   struct pcm_desc descriptor
+	 *   char *version
+	 */
+
+	/* Firmware size */
+	offset = 0;
+	copy_size = sizeof(firmware_size);
+	memcpy(&firmware_size, mcu->load_buffer + offset, copy_size);
+	printk(BIOS_DEBUG, "SPM: binary array size = %#x\n", firmware_size);
+
+	/* Binary */
+	offset = SPMFW_HEADER_SIZE; /* binary start offset */
+	copy_size = firmware_size * sizeof(u32);
+	assert(offset < file_size);
+	pcm->buf = (u8 *)(mcu->load_buffer + offset);
+
+	/* Descriptor */
+	offset += copy_size;
+	assert(offset < file_size);
+	copy_size = sizeof(pcm->desc);
+	memcpy(&pcm->desc, mcu->load_buffer + offset, copy_size);
+
+	/* Firmware size and total words need to be the same */
+	assert(firmware_size == pcm->desc.total_words);
+
+	/* Version */
+	offset += copy_size;
+	assert(offset < file_size);
+	printk(BIOS_INFO, "SPM: spmfw (version %s)\n", (u8 *)mcu->load_buffer + offset);
+}
+
+static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
+{
+	u32 val, mask;
+
+	/* Toggle event counter clear */
+	setbits32(&mtk_spm->pcm_con1,
+		  SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
+
+	/* Toggle for reset SYS TIMER start point */
+	setbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB);
+
+	if (pwrctrl->timer_val_cust == 0)
+		val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
+	else
+		val = pwrctrl->timer_val_cust;
+
+	write32(&mtk_spm->pcm_timer_val, val);
+
+	/* Disable pcm timer */
+	clrsetbits32(&mtk_spm->pcm_con1,
+		     RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
+
+	/* Unmask AP wakeup source */
+	if (pwrctrl->wake_src_cust == 0)
+		mask = pwrctrl->wake_src;
+	else
+		mask = pwrctrl->wake_src_cust;
+
+	if (pwrctrl->reg_csyspwrreq_mask)
+		mask &= ~SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B;
+
+	write32(&mtk_spm->spm_wakeup_event_mask, ~mask);
+
+	/* Unmask SPM ISR (keep TWAM setting) */
+	setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX);
+
+	/* Toggle event counter clear */
+	clrsetbits32(&mtk_spm->pcm_con1,
+		     SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY);
+
+	/* Toggle for reset SYS TIMER start point */
+	clrbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB);
+}
+
+static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
+{
+	u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1;
+
+	/* Set PCM flags and data */
+	if (pwrctrl->pcm_flags_cust_clr != 0)
+		pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
+	if (pwrctrl->pcm_flags_cust_set != 0)
+		pcm_flags |= pwrctrl->pcm_flags_cust_set;
+	if (pwrctrl->pcm_flags1_cust_clr != 0)
+		pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
+	if (pwrctrl->pcm_flags1_cust_set != 0)
+		pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
+
+	write32(&mtk_spm->spm_sw_flag_0, pcm_flags);
+	write32(&mtk_spm->spm_sw_flag_1, pcm_flags1);
+	write32(&mtk_spm->spm_sw_rsv_7, pcm_flags);
+	write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1);
+}
+
+static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
+{
+	/* Waiting for loading SPMFW done*/
+	while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0)
+		;
+
+	/* Init register to match PCM expectation */
+	write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF);
+	write32(&mtk_spm->spm_bus_protect2_mask_b,
+		SPM_BUS_PROTECT2_MASK_B_DEF);
+	write32(&mtk_spm->pcm_reg_data_ini, 0);
+
+	spm_set_pcm_flags(pwrctrl);
+
+	/* Kick PCM to run (only toggle PCM_KICK) */
+	setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+
+	/* Reset md32pcm */
+	setbits32(&mtk_spm->md32pcm_cfgreg_sw_rstn,
+		  MD32PCM_CFGREG_SW_RSTN_RESET);
+
+	/* Waiting for SPM init done */
+	udelay(SPM_INIT_DONE_US);
+}
+
+static void reset_spm(struct mtk_mcu *mcu)
+{
+	struct dyna_load_pcm *pcm = (struct dyna_load_pcm *)mcu->priv;
+
+	spm_parse_firmware(mcu);
+	spm_reset_and_init_pcm();
+	spm_kick_im_to_fetch(pcm);
+	spm_init_pcm_register();
+	spm_set_wakeup_event(&spm_init_ctrl);
+	spm_kick_pcm_to_run(&spm_init_ctrl);
+}
+
+static struct mtk_mcu spm = {
+	.firmware_name = CONFIG_SPM_FIRMWARE,
+	.reset = reset_spm,
+};
+
+int spm_init(void)
+{
+	struct dyna_load_pcm pcm;
+	struct stopwatch sw;
+
+	stopwatch_init(&sw);
+
+	spm_register_init();
+	spm_set_power_control(&spm_init_ctrl);
+	spm_set_sysclk_settle();
+
+	spm.load_buffer = _dram_dma;
+	spm.buffer_size = REGION_SIZE(dram_dma);
+	spm.priv = (void *)&pcm;
+
+	if (mtk_init_mcu(&spm)) {
+		printk(BIOS_ERR, "SPM: %s: failed in mtk_init_mcu\n", __func__);
+		return -1;
+	}
+
+	printk(BIOS_INFO, "SPM: %s done in %ld msecs, spm pc = %#x\n",
+	       __func__, stopwatch_duration_msecs(&sw),
+	       read32(&mtk_spm->md32pcm_pc));
+
+	return 0;
+}