Attention is currently required from: Federico Amedeo Izzo, Felix Singer.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email )
Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1) ......................................................................
Patch Set 10:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82010/comment/5ab0d110_fcc5390e : PS10, Line 57: Patchset 5: Re-enabled dptf, added default options to Kconfig. : Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works : Pa
It's not needed to document the changes of each patchset. Please remove.
Doesn't hurt, and it's common practice in mailing lists commits.
File src/mainboard/aoostar/wtr_r1/bootblock.c:
https://review.coreboot.org/c/coreboot/+/82010/comment/76d7cee0_ca20571d : PS10, Line 20: ite_set_3vsbsw(GPIO_DEV, true); Where do the Super I/O settings come from?
On the IT8625E (closest chip for which I have a datasheet), GP40 is muxed with 3VSBSW#. Since you're configuring GP40 as a GPIO, this doesn't seem to have any effect. I would recommend double-checking these settings, as this can cause the board to misbehave.
https://review.coreboot.org/c/coreboot/+/82010/comment/43d421f4_94d03208 : PS10, Line 21: ite_delay_pwrgd3(GPIO_DEV); There's very few boards that use this, is it actually needed? Hard to say without testing S3, though.
File src/mainboard/aoostar/wtr_r1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/82010/comment/59d3b05c_35771ed3 : PS10, Line 117: .clk_req = 2, How were CLKSRC and CLKREQ values determined? These could be causing troubles with power management.
File src/mainboard/aoostar/wtr_r1/gpio.h:
https://review.coreboot.org/c/coreboot/+/82010/comment/0dd6be0c_e003e5db : PS10, Line 207: _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PWRBTN# */ Try this instead: `PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1)`
If this doesn't work, you can try different settings for pad reset (`PWROK`, `DEEP`, `PLTRST`, `RSMRST`; the current `_PAD_CFG_STRUCT` values correspond to `PWROK` for reset).