Change in coreboot[master]: soc/intel/alderlake: Configure DDR5 Physical channel width to 64

[Eric Lai (Code Review)]

Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Meera Ravindranath, Subrata Banik, Ronak Kanabar, Patrick Rudolph.
Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52730 )

Change subject: soc/intel/alderlake: Configure DDR5 Physical channel width to 64
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Patch Set 8:

(2 comments)

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/52730/comment/66201811_47d9d8a4 
PS8, Line 15: #define DDR5_CHANNELS			CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH)
> I see your point, Nico. EDS vol. 1 does seem to indicates it is always effectively 128 bits wide […]

I assume original calculation will mislead the dimms calculation. https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thir...

https://review.coreboot.org/c/coreboot/+/52730/comment/de3b0041_a838f342 
PS8, Line 15: CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH)
divided physical channel by 2 is more match the EDS. @Meera, could you try that work or not?